library ieee;
use ieee.std_logic_1164.all;
entity mux2to1_9 is
generic(n:integer:=9);
port(s    :in  std_logic;
     in_0 :in  std_logic_vector(n-1 downto 0);
     in_1 :in  std_logic_vector(n-1 downto 0);
     out_y:out std_logic_vector(n-1 downto 0));
end entity mux2to1_9;
architecture behave of mux2to1_9 is
begin
  with s select
    out_y<=in_0 when '0',
	        in_1 when others;
end architecture behave;