?? mem_interface_top_ddr_controller_0.txt
字號:
if ( (rfc_count == 6'b00001) && (conflict_detect_r) )begin
next_state = ACTIVE;
end else if (rfc_count == 6'b00001) begin
next_state = IDLE;
end else begin
next_state = AUTO_REFRESH_WAIT;
end
end
ACTIVE : next_state = ACTIVE_WAIT;
ACTIVE_WAIT : begin
if (rcd_count == 3'b000) begin
if(WR)
next_state = FIRST_WRITE;
else if (RD)
next_state = FIRST_READ;
else
next_state = IDLE;
end
else
next_state = ACTIVE_WAIT;
end // case: `active_wait
FIRST_WRITE : begin
if(((conflict_detect & (~conflict_resolved_r))|| auto_ref) || RD)
next_state = WRITE_WAIT;
else if((burst_cnt == 3'd1) && WR)
next_state = BURST_WRITE;
else
next_state = WRITE_WAIT;
end
BURST_WRITE : begin
if(((conflict_detect & (~conflict_resolved_r))|| auto_ref) || RD)
next_state = WRITE_WAIT;
else if((burst_cnt == 3'd1) && WR)
next_state = BURST_WRITE;
else
next_state = WRITE_WAIT;
end
WRITE_WAIT : begin
if ((conflict_detect & (~conflict_resolved_r))|| auto_ref) begin
if ((wtp_count == 4'b0000) && (ras_count == 4'b0000))
next_state = PRECHARGE;
else
next_state = WRITE_WAIT;
end else if (RD ) begin
next_state = WRITE_READ;
end else if ((WR) && (wrburst_cnt == 3'b010)) begin
next_state = BURST_WRITE;
end else if((WR) && (wrburst_cnt == 3'b000)) begin
next_state = FIRST_WRITE;
end else if (idle_cnt == 4'b0000) begin
next_state = PRECHARGE;
end else begin
next_state = WRITE_WAIT;
end
end
WRITE_READ : begin
if (wr_to_rd_count == 4'b0000) begin
next_state = FIRST_READ;
end else begin
next_state = WRITE_READ;
end
end
FIRST_READ :begin
if(((conflict_detect & (~conflict_resolved_r))|| auto_ref) || WR)
next_state = READ_WAIT;
else if((burst_cnt == 3'd1) && RD)
next_state = BURST_READ;
else
next_state = READ_WAIT;
end
BURST_READ :begin
if(((conflict_detect & (~conflict_resolved_r))|| auto_ref) || WR)
next_state = READ_WAIT;
else if((burst_cnt == 3'd1) && RD)
next_state = BURST_READ;
else
next_state = READ_WAIT;
end
READ_WAIT : begin
if ((conflict_detect & (~conflict_resolved_r)) || auto_ref) begin
if(rtp_count == 4'b0000 && ras_count == 4'b0000)
next_state = PRECHARGE;
else
next_state = READ_WAIT;
end else if (WR) begin
next_state = READ_WRITE;
end else if ((RD) && (read_burst_cnt <= 3'b010)) begin
if(af_empty_r)
next_state = FIRST_READ;
else
next_state = BURST_READ;
end else if (idle_cnt == 4'b0000) begin
next_state = PRECHARGE;
end else begin
next_state = READ_WAIT;
end
end
READ_WRITE : begin
if (rd_to_wr_count == 4'b0000) begin
next_state = FIRST_WRITE;
end else begin
next_state = READ_WRITE;
end
end
endcase
end
//register command outputs
always @ (posedge clk_0) begin
if (rst_r) begin
state_r2 <= 5'b00000;
state_r3 <= 5'b00000;
end
else begin
state_r2 <= state;
state_r3 <= state_r2;
end
end
always @ (posedge clk_0) begin
if (rst_r) begin
init_state_r2 <= 5'b00000;
init_state_r3 <= 5'b00000;
end
else begin
init_state_r2 <= init_state;
init_state_r3 <= init_state_r2;
end
end
// commands to the memory
always @ (posedge clk_0) begin
if (rst_r) begin
ddr_ras_r <= 1'b1;
end
else if (state == LOAD_MODE_REG_ST || state == PRECHARGE || state ==ACTIVE
|| state == AUTO_REFRESH || init_state==INIT_LOAD_MODE_REG_ST ||
init_state == INIT_PRECHARGE || init_state == INIT_AUTO_REFRESH
|| init_state == INIT_DUMMY_ACTIVE) begin
ddr_ras_r <= 1'b0;
end
else ddr_ras_r <= 1'b1;
end
// commands to the memory
always @ (posedge clk_0) begin
if (rst_r)
ddr_cas_r <= 1'b1;
else if (state == LOAD_MODE_REG_ST || init_state == INIT_LOAD_MODE_REG_ST
|| read_write_state || init_state == INIT_DUMMY_FIRST_READ ||
dummy_write_state || state==AUTO_REFRESH ||
init_state == INIT_AUTO_REFRESH || init_state== INIT_DUMMY_READ
|| pattern_read_state)
ddr_cas_r <= 1'b0;
else if ((state == ACTIVE_WAIT) || (init_state == INIT_DUMMY_ACTIVE_WAIT))
ddr_cas_r <= 1'b1;
else
ddr_cas_r <= 1'b1;
end // always @ (posedge clk_0)
// commands to the memory
always @ (posedge clk_0) begin
if (rst_r)
ddr_we_r <= 1'b1;
else if (state == LOAD_MODE_REG_ST || state == PRECHARGE ||
init_state==INIT_LOAD_MODE_REG_ST || init_state==INIT_PRECHARGE ||
write_state || dummy_write_state)
ddr_we_r <= 1'b0;
else
ddr_we_r <= 1'b1;
end
//register commands to the memory
always @ (posedge clk_0) begin
if (rst_r) begin
ddr_ras_r2 <= 1'b1;
ddr_cas_r2 <= 1'b1;
ddr_we_r2 <= 1'b1;
end
else begin
ddr_ras_r2 <= ddr_ras_r;
ddr_cas_r2 <= ddr_cas_r;
ddr_we_r2 <= ddr_we_r;
end
end
//register commands to the memory
always @ (posedge clk_0) begin
if (rst_r)
begin
ddr_ras_r3 <= 1'b1;
ddr_cas_r3 <= 1'b1;
ddr_we_r3 <= 1'b1;
end
else begin
ddr_ras_r3 <= ddr_ras_r2;
ddr_cas_r3 <= ddr_cas_r2;
ddr_we_r3 <= ddr_we_r2;
end // else: !if(rst_r)
end // always @ (posedge clk_0)
always @ (posedge clk_0) begin
if (rst_r)
row_addr_r[`row_address-1:0] <= `row_address'h0;
else
row_addr_r[`row_address-1:0] <= af_addr[(`row_address + `col_ap_width)-1
:`col_ap_width];
end
// chip enable generation logic
always @ (posedge clk_0) begin
if (rst_r)
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'h0;
else begin
if (af_addr_r[`chip_address + `bank_address +`row_address+
`col_ap_width-1:`bank_address+`row_address+`col_ap_width]
== `chip_address'h0) begin
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'hE;
end else if (af_addr_r[`chip_address + `bank_address +`row_address +
`col_ap_width-1:`bank_address +`row_address +
`col_ap_width] == `chip_address'h1) begin
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'hD;
end else if (af_addr_r[`chip_address + `bank_address +`row_address +
`col_ap_width-1:`bank_address +`row_address +
`col_ap_width] == `chip_address'h2) begin
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'hB;
end else if (af_addr_r[`chip_address + `bank_address +`row_address +
`col_ap_width-1:`bank_address +`row_address +
`col_ap_width] == `chip_address'h3) begin
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'h7;
end else
ddr_cs_r[`no_of_cs-1 : 0] <= `no_of_cs'hF;
end // else: !if(rst_r)
end // always@ (posedge clk_0)
// address during init
always @ (posedge clk_0) begin
if (rst_r)
ddr_address_init_r <= `row_address'h0000;
else if (init_memory) begin
if (init_state_r2 == INIT_PRECHARGE)
ddr_address_init_r <= `row_address'h0400; //A10= 1 for precharge all
else if ( init_state_r2 == INIT_LOAD_MODE_REG_ST && init_count_cp == 4'h3)
ddr_address_init_r <= ext_mode_reg; // A0 == 0 for DLL enable
else if ( init_state_r2 == INIT_LOAD_MODE_REG_ST && init_count_cp == 4'h4 )
ddr_address_init_r <= (`row_address'h0100 | load_mode_reg);// A8 == 1
//for DLL reset
else if ( init_state_r2 == INIT_LOAD_MODE_REG_ST && init_count_cp == 4'h9 )
ddr_address_init_r <= (`row_address'hFEFF & load_mode_reg);// A8 = 0
//for DLL reset bit to deactivate
else
ddr_address_init_r <= `row_address'h0000;
end
end // always @ (posedge clk_0)
always @ (posedge clk_0) begin
if (rst_r)
ddr_address_r1 <= `row_address'h0000;
else if ((init_state_r2 == INIT_DUMMY_WRITE1) ||
(init_state_r2 == INIT_PATTERN_READ1))
ddr_address_r1 <= `row_address'h0000;
else if ((init_state_r2 == INIT_DUMMY_WRITE2) ||
(init_state_r2 == INIT_PATTERN_READ2))
ddr_address_r1 <= ddr_address_BL;
else if ((state_r2 == ACTIVE))
ddr_address_r1 <= row_addr_r;
else if (read_write_state_r2)
ddr_address_r1 <= af_addr_r[`row_address-1 :0] & `row_address'hFBFF;
// Auto Precharge option is disabled
else if (state_r2 == PRECHARGE || init_state_r2 == INIT_PRECHARGE) begin
ddr_address_r1 <= `row_address'h0400;
end
else if (state_r2 == LOAD_MODE_REG_ST ||
init_state_r2 == INIT_LOAD_MODE_REG_ST)
ddr_address_r1 <= af_addr_r[`row_address-1:0];
else ddr_address_r1 <= `row_address'h0000;
end // always @ (posedge clk_0)
always @ (posedge clk_0) begin
if (rst_r)
ddr_address_r2 <= `row_address'h0000;
else
begin
if(init_memory)
ddr_address_r2 <= ddr_address_init_r;
else
ddr_address_r2 <= ddr_address_r1;
end
end
always @ (posedge clk_0) begin
if (rst_r) begin
ddr_ba_r1[`bank_address-1:0] <= `bank_address'h0;
end
else if (init_memory == 1'b1 && (state_r2 == LOAD_MODE_REG_ST ||
init_state_r2 == INIT_LOAD_MODE_REG_ST)) begin
if (init_count_cp == 4'h3)
ddr_ba_r1[`bank_address-1:0] <= `bank_address'h1;
else ddr_ba_r1[`bank_address-1:0] <= `bank_address'h0;
end else if ((state_r2 == ACTIVE)|| (init_state_r2 == INIT_DUMMY_ACTIVE)
|| (state_r2==LOAD_MODE_REG_ST) ||
(init_state_r2==INIT_LOAD_MODE_REG_ST) ||
((state_r2==PRECHARGE) || (init_state_r2 == INIT_PRECHARGE)
& PRE_r))
ddr_ba_r1[`bank_address-1:0] <= af_addr[(`bank_address+`row_address +
`col_ap_width)-1:(`col_ap_width + `row_address)];
else ddr_ba_r1[`bank_address-1:0] <= ddr_ba_r1[`bank_address-1:0];
end
always @ (posedge clk_0) begin
if (rst_r)
ddr_ba_r2 <= `bank_address'h0;
else
ddr_ba_r2 <= ddr_ba_r1;
end
always @ (posedge clk_0) begin
if (rst_r)
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'h0;
else if (init_memory == 1'b1 ) begin
if (chip_cnt == 2'h0)
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'hE;
else if (chip_cnt == 2'h1)
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'hD;
else if (chip_cnt == 2'h2)
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'hB;
else if (chip_cnt == 2'h3)
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'h7;
else
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'hF;
end
else if ((state_r3 == AUTO_REFRESH ) || (init_state_r3 == INIT_AUTO_REFRESH ))
ddr_cs_r1[`no_of_cs-1:0] <= `no_of_cs'h0;
else if ((state_r3 == ACTIVE )||(init_state_r3 == INIT_DUMMY_ACTIVE)||
(state_r3==LOAD_MODE_REG_ST) ||
(init_state_r3==INIT_LOAD_MODE_REG_ST)
||(state_r3 == PRECHARGE_WAIT) ||
(init_state_r3 == INIT_PRECHARGE_WAIT))
ddr_cs_r1[`no_of_cs-1:0] <= ddr_cs_r[`no_of_cs-1:0];
else
ddr_cs_r1[`no_of_cs-1:0] <= ddr_cs_r1[`no_of_cs-1:0];
end // always @ (posedge clk_0)
always @ (posedge clk_0) begin
if (rst_r)
conflict_resolved_r <= 1'b0;
else begin
if (((state == PRECHARGE_WAIT) || (init_state == INIT_PRECHARGE_WAIT))
& conflict_detect_r)
conflict_resolved_r <= 1'b1;
else if(af_rden)
conflict_resolved_r <= 1'b0;
end
end
always @ (posedge clk_0) begin
if (rst_r)
ddr_cke_r<= `cke_width'h0;
else begin
if(done_200us == 1'b1)
ddr_cke_r<= `cke_width'hF;
end
end
assign ctrl_ddr_address[`row_address-1:0] = ddr_address_r2[`row_address-1:0];
assign ctrl_ddr_ba [`bank_address-1:0] = ddr_ba_r2[`bank_address-1:0];
assign ctrl_ddr_ras_L = ddr_ras_r3;
assign ctrl_ddr_cas_L = ddr_cas_r3;
assign ctrl_ddr_we_L = ddr_we_r3;
assign ctrl_ddr_cs_L = 2'b00;
assign ctrl_ddr_cke = ddr_cke_r;
endmodule
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