///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_data_path_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantiates the tap logic and the data write modules. Gives
//              the rise and the fall data and the calibration information
//              for the IDELAY elements.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_data_path_0
  (
   input                                CLK,
   input                                CLK90,
   input                                RESET0,
   input                                RESET90,
   input                                idelay_ctrl_rdy,
   input                                CTRL_DUMMYREAD_START,
   input [(`data_width*2)-1:0]          WDF_DATA,
   input [(`data_mask_width*2)-1:0]     MASK_DATA,
   input                                dummy_write_pattern,
   input                                CTRL_WREN,
   input                                CTRL_DQS_RST,
   input                                CTRL_DQS_EN,
   input [`data_strobe_width-1:0]       dqs_delayed,
   output [`ReadEnable-1:0]             data_idelay_inc,
   output [`ReadEnable-1:0]             data_idelay_ce,
   output [`ReadEnable-1:0]             data_idelay_rst,
   output [`ReadEnable-1:0]             dqs_idelay_inc,
   output [`ReadEnable-1:0]             dqs_idelay_ce,
   output [`ReadEnable-1:0]             dqs_idelay_rst,
   output                               SEL_DONE,
   output                               dqs_rst,
   output                               dqs_en,
   output                               wr_en,
   output [`data_width-1:0]             wr_data_rise,
   output [`data_width-1:0]             wr_data_fall,
   output [`data_mask_width-1:0]        mask_data_rise,
   output [`data_mask_width-1:0]        mask_data_fall
   );

mem_interface_top_data_write_0 data_write_10
  (
   .CLK                 (CLK),
   .CLK90               (CLK90),
   .RESET0              (RESET0),
   .RESET90             (RESET90),
   .WDF_DATA            (WDF_DATA),
   .MASK_DATA           (MASK_DATA),
   .dummy_write_pattern (dummy_write_pattern),
   .CTRL_WREN           (CTRL_WREN),
   .CTRL_DQS_RST        (CTRL_DQS_RST),
   .CTRL_DQS_EN         (CTRL_DQS_EN),
   .dqs_rst             (dqs_rst),
   .dqs_en              (dqs_en),
   .wr_en               (wr_en),
   .wr_data_rise        (wr_data_rise),
   .wr_data_fall        (wr_data_fall),
   .mask_data_rise      (mask_data_rise),
   .mask_data_fall      (mask_data_fall)
   );

mem_interface_top_tap_logic_0 tap_logic_00
  (
   .CLK                  (CLK),
   .RESET0               (RESET0),
   .idelay_ctrl_rdy      (idelay_ctrl_rdy),
   .CTRL_DUMMYREAD_START (CTRL_DUMMYREAD_START),
   .dqs_delayed          (dqs_delayed),
   .data_idelay_inc      (data_idelay_inc),
   .data_idelay_ce       (data_idelay_ce),
   .data_idelay_rst      (data_idelay_rst),
   .dqs_idelay_inc       (dqs_idelay_inc),
   .dqs_idelay_ce        (dqs_idelay_ce),
   .dqs_idelay_rst       (dqs_idelay_rst),
   .SEL_DONE             (SEL_DONE)
   );

endmodule