///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_pattern_compare8.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Compares the IOB output 4 bit data of one bank that is read data
//              during the intilaization to get the delay for the data with 
//              respect to the command issued.
///////////////////////////////////////////////////////////////////////////////


`timescale 1ns / 1ps


module mem_interface_top_pattern_compare8
  (
   input           clk,
   input           rst,
   input           ctrl_rden,
   input [7:0]     rd_data_rise,
   input [7:0]     rd_data_fall,
   output          comp_done,
   output reg      first_rising,
   output [2:0]    rise_clk_count,
   output [2:0]    fall_clk_count
   );


   reg [1:0] 		     state_rise;
   reg [1:0] 		     next_state_rise;
   reg [1:0] 		     state_fall;
   reg [1:0] 		     next_state_fall;
   reg [2:0] 		     rise_clk_cnt;
   reg [2:0] 		     fall_clk_cnt;
   reg 			     ctrl_rden_r ;
   reg 			     rst_r;
   reg [7:0] 		     rd_data_rise_r2;
   reg [7:0] 		     rd_data_fall_r2;
   wire [7:0] 		     pattern_rise1;
   wire [7:0] 		     pattern_fall1;
   wire [7:0] 		     pattern_rise2;
   wire [7:0] 		     pattern_fall2;

   localparam 		     idle        = 2'b00;
   localparam 		     first_data  = 2'b01;
   localparam 		     second_data = 2'b10;
   localparam 		     comp_over   = 2'b11;

   assign 		     pattern_rise1 = 8'hAA;
   assign 		     pattern_fall1 = 8'h55;
   assign 		     pattern_rise2 = 8'h99;
   assign 		     pattern_fall2 = 8'h66;

   always @(posedge clk)
     rst_r <= rst;

   always @(posedge clk) begin
      if(rst_r)
        state_rise <= idle;
      else
        state_rise <= next_state_rise;
   end

   always @(posedge clk) begin
      if(rst_r)
        state_fall <= idle;
      else
        state_fall <= next_state_fall;
   end

   always @(posedge clk) begin
      if(rst_r)
        ctrl_rden_r <= 1'b0;
      else
        ctrl_rden_r <= ctrl_rden;
   end

   always @(posedge clk) begin
      if(rst_r)
        rise_clk_cnt <= 3'b000;
      else if((state_rise == first_data ) || (state_rise == second_data ))
        rise_clk_cnt <= rise_clk_cnt + 1;
   end

   assign rise_clk_count = (state_rise == comp_over) ? rise_clk_cnt : 3'b000;

   assign comp_done = (state_rise == comp_over) && (state_fall == comp_over);

   always @(posedge clk) begin
      if(rst_r)
        fall_clk_cnt <= 3'b000;
      else if((state_fall == first_data ) || (state_fall == second_data ))
        fall_clk_cnt <= fall_clk_cnt + 1;
   end

   assign fall_clk_count = (state_fall == comp_over) ? fall_clk_cnt : 3'b000;

   always @(posedge clk) begin
      if(rst_r)
        first_rising <= 1'b0;
      else if(state_rise == second_data && rd_data_rise == pattern_fall2)
        first_rising <= 1'b1;
   end

   always @(posedge clk) begin
      if(rst_r) begin
	 rd_data_rise_r2 <= 8'h0;
	 rd_data_fall_r2 <= 8'h0;
      end
      else begin
	 rd_data_rise_r2 <= rd_data_rise;
	 rd_data_fall_r2 <= rd_data_fall;
      end
   end

   always @(ctrl_rden_r or state_rise or rd_data_rise or rd_data_rise_r2 or
	    pattern_rise1 or pattern_fall1 or pattern_rise2 or pattern_fall2 
	    or rst_r) begin
      if(rst_r)
        next_state_rise <= idle;
      else
	begin
           case (state_rise)
             idle :
               begin
                  if(ctrl_rden_r)
                    next_state_rise <= first_data;
                  else
                    next_state_rise <= idle;
               end

             first_data :
               begin
                  if((rd_data_rise == pattern_rise1) || (rd_data_rise == pattern_fall1))
                    next_state_rise <= second_data;
                  else
                    next_state_rise <= first_data;
               end

             second_data :
               begin
                  if(((rd_data_rise == pattern_rise2) && (rd_data_rise_r2 == pattern_rise1)) ||
                     ((rd_data_rise == pattern_fall2) && (rd_data_rise_r2 == pattern_fall1)))
                    next_state_rise <= comp_over;
                  else
                    next_state_rise <= second_data;
               end

             comp_over :
               next_state_rise <= comp_over;

             default :
               next_state_rise <= idle;
           endcase
	end
   end

   always @(ctrl_rden_r or state_fall or rd_data_fall or rd_data_fall_r2 or 
	    pattern_fall1 or pattern_rise1 or pattern_fall2 or pattern_rise2 
	    or rst_r) begin
      if(rst_r)
        next_state_fall <= idle;
      else
	begin
           case (state_fall)
             idle :
               begin
                  if(ctrl_rden_r)
                    next_state_fall <= first_data;
                  else
                    next_state_fall <= idle;
               end

             first_data :
               begin
                  if((rd_data_fall == pattern_fall1) || (rd_data_fall == pattern_rise1))
                    next_state_fall <= second_data;
                  else
                    next_state_fall <= first_data;
               end

             second_data :
               begin
                  if(((rd_data_fall == pattern_rise2) && (rd_data_fall_r2 == pattern_rise1)) ||
                     ((rd_data_fall == pattern_fall2) && (rd_data_fall_r2 == pattern_fall1)))
                    next_state_fall <= comp_over;
                  else
                    next_state_fall <= second_data;
               end

             comp_over :
               next_state_fall <= comp_over;

             default :
               next_state_fall <= idle;
           endcase
	end
   end

endmodule