# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
# XST (Creating Lso File) : 
getinstr.lso
# xst flow : RunXST
getinstr.syr
getinstr.prj
getinstr.sprj
getinstr.ana
getinstr.stx
getinstr.cmd_log
getinstr.ngc
getinstr.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
getinstr.ngc
getinstr.ngr
cpu.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
getinstr.ngc
getinstr.ngr
cpu.ngr
# ProjNav -> New Source -> TBW
f:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
alu.lso
# xst flow : RunXST
alu.syr
alu.prj
alu.sprj
alu.ana
alu.stx
alu.cmd_log
alu.ngc
alu.ngr
# ModelSim : Simulate Behavioral VHDL Model
walu.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
F:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
exe.lso
# xst flow : RunXST
exe.syr
exe.prj
exe.sprj
exe.ana
exe.stx
exe.cmd_log
alu.ngc
exe.ngc
alu.ngr
exe.ngr
# ModelSim : Simulate Behavioral VHDL Model
wexe.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wexe.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
wexe.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
exe.lso
# xst flow : RunXST
exe.syr
exe.prj
exe.sprj
exe.ana
exe.stx
exe.cmd_log
alu.ngc
exe.ngc
alu.ngr
exe.ngr
# XST (Creating Lso File) : 
exe.lso
# xst flow : RunXST
exe.syr
exe.prj
exe.sprj
exe.ana
exe.stx
exe.cmd_log
alu.ngc
exe.ngc
alu.ngr
exe.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wexe.vhw
wexe.ano
wexe.tfw
# ModelSim : Simulate Behavioral VHDL Model
wexe.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
F:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wGetInstr.vhw
wGetInstr.ano
wGetInstr.tfw
# ModelSim : Simulate Behavioral VHDL Model
wGetInstr.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
getinstr.lso
# xst flow : RunXST
getinstr.syr
getinstr.prj
getinstr.sprj
getinstr.ana
getinstr.stx
getinstr.cmd_log
getinstr.ngc
getinstr.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wGetInstr.vhw
wGetInstr.ano
wGetInstr.tfw
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wGetInstr.vhw
wGetInstr.ano
wGetInstr.tfw
# ModelSim : Simulate Behavioral VHDL Model
wGetInstr.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
memcontrol.lso
# xst flow : RunXST
memcontrol.syr
memcontrol.prj
memcontrol.sprj
memcontrol.ana
memcontrol.stx
memcontrol.cmd_log
memcontrol.ngc
memcontrol.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
timer.lso
# xst flow : RunXST
timer.syr
timer.prj
timer.sprj
timer.ana
timer.stx
timer.cmd_log
timer.ngc
timer.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# ProjNav -> New Source -> TBW
F:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
wmemcontrol.vhw
wmemcontrol.ano
wmemcontrol.tfw
# ModelSim : Simulate Behavioral VHDL Model
wmemcontrol.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# XST (Creating Lso File) : 
alu.lso
# xst flow : RunXST
alu.syr
alu.prj
alu.sprj
alu.ana
alu.stx
alu.cmd_log
alu.ngc
alu.ngr
# XST (Creating Lso File) : 
alu.lso
# xst flow : RunXST
alu.syr
alu.prj
alu.sprj
alu.ana
alu.stx
alu.cmd_log
alu.ngc
alu.ngr
# XST (Creating Lso File) : 
exe.lso
# xst flow : RunXST
exe.syr
exe.prj
exe.sprj
exe.ana
exe.stx
exe.cmd_log
alu.ngc
exe.ngc
alu.ngr
exe.ngr
# XST (Creating Lso File) : 
exe.lso
# xst flow : RunXST
exe.syr
exe.prj
exe.sprj
exe.ana
exe.stx
exe.cmd_log
alu.ngc
exe.ngc
alu.ngr
exe.ngr
# XST (Creating Lso File) : 
getinstr.lso
# xst flow : RunXST
getinstr.syr
getinstr.prj
getinstr.sprj
getinstr.ana
getinstr.stx
getinstr.cmd_log
getinstr.ngc
getinstr.ngr
# XST (Creating Lso File) : 
memcontrol.lso
# xst flow : RunXST
memcontrol.syr
memcontrol.prj
memcontrol.sprj
memcontrol.ana
memcontrol.stx
memcontrol.cmd_log
memcontrol.ngc
memcontrol.ngr
# XST (Creating Lso File) : 
timer.lso
# xst flow : RunXST
timer.syr
timer.prj
timer.sprj
timer.ana
timer.stx
timer.cmd_log
timer.ngc
timer.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# ProjNav -> New Source -> TBW
F:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tcpu.vhw
tcpu.ano
tcpu.tfw
# ModelSim : Simulate Behavioral VHDL Model
tcpu.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tcpu.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tcpu.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
F:\cpu\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tcpu1.vhw
tcpu1.ano
tcpu1.tfw
# ModelSim : Simulate Behavioral VHDL Model
tcpu1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tcpu1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\cpu/_ngo
cpu.ngd
cpu_ngdbuild.nav
cpu.bld
Wcpu.ucf.untf
cpu.cmd_log
# XST (Creating Lso File) : 
memcontrol.lso
# xst flow : RunXST
memcontrol.syr
memcontrol.prj
memcontrol.sprj
memcontrol.ana
memcontrol.stx
memcontrol.cmd_log
memcontrol.ngc
memcontrol.ngr
# XST (Creating Lso File) : 
memcontrol.lso
# xst flow : RunXST
memcontrol.syr
memcontrol.prj
memcontrol.sprj
memcontrol.ana
memcontrol.stx
memcontrol.cmd_log
memcontrol.ngc
memcontrol.ngr
# XST (Creating Lso File) : 
memcontrol.lso
# xst flow : RunXST
memcontrol.syr
memcontrol.prj
memcontrol.sprj
memcontrol.ana
memcontrol.stx
memcontrol.cmd_log
memcontrol.ngc
memcontrol.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\cpu/_ngo
cpu.ngd
cpu_ngdbuild.nav
cpu.bld
Wcpu.ucf.untf
cpu.cmd_log
# Implementation : Map
cpu_map.ncd
cpu.ngm
cpu.pcf
cpu.nc1
cpu.mrp
cpu_map.mrp
cpu.mdf
__projnav/map.log
cpu.cmd_log
MAP_NO_GUIDE_FILE_CPF "cpu"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
cpu.twr
cpu.twx
cpu.tsi
cpu.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
cpu.ncd
cpu.par
cpu.pad
cpu_pad.txt
cpu_pad.csv
cpu.pad_txt
cpu.dly
reportgen.log
cpu.xpi
cpu.grf
cpu.itr
cpu_last_par.ncd
__projnav/par.log
cpu.placed_ncd_tracker
cpu.routed_ncd_tracker
cpu.cmd_log
PAR_NO_GUIDE_FILE_CPF "cpu"
# Generate Programming File
__projnav/cpu_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
cpu.ut
# Generate Programming File
cpu.bgn
cpu.rbt
cpu.ll
cpu.msk
cpu.drc
cpu.nky
cpu.bit
cpu.bin
cpu.isc
cpu.cmd_log
# Generate Programming File
__projnav/cpu_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
cpu.ut
# Generate Programming File
cpu.bgn
cpu.rbt
cpu.ll
cpu.msk
cpu.drc
cpu.nky
cpu.bit
cpu.bin
cpu.isc
cpu.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\cpu/_ngo
cpu.ngd
cpu_ngdbuild.nav
cpu.bld
Wcpu.ucf.untf
cpu.cmd_log
# Implementation : Map
cpu_map.ncd
cpu.ngm
cpu.pcf
cpu.nc1
cpu.mrp
cpu_map.mrp
cpu.mdf
__projnav/map.log
cpu.cmd_log
MAP_NO_GUIDE_FILE_CPF "cpu"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
cpu.twr
cpu.twx
cpu.tsi
cpu.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
cpu.ncd
cpu.par
cpu.pad
cpu_pad.txt
cpu_pad.csv
cpu.pad_txt
cpu.dly
reportgen.log
cpu.xpi
cpu.grf
cpu.itr
cpu_last_par.ncd
__projnav/par.log
cpu.placed_ncd_tracker
cpu.routed_ncd_tracker
cpu.cmd_log
PAR_NO_GUIDE_FILE_CPF "cpu"
# Generate Programming File
__projnav/cpu_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
cpu.ut
# Generate Programming File
cpu.bgn
cpu.rbt
cpu.ll
cpu.msk
cpu.drc
cpu.nky
cpu.bit
cpu.bin
cpu.isc
cpu.cmd_log
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\cpu/_ngo
cpu.ngd
cpu_ngdbuild.nav
cpu.bld
Wcpu.ucf.untf
cpu.cmd_log
# Implementation : Map
cpu_map.ncd
cpu.ngm
cpu.pcf
cpu.nc1
cpu.mrp
cpu_map.mrp
cpu.mdf
__projnav/map.log
cpu.cmd_log
MAP_NO_GUIDE_FILE_CPF "cpu"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
cpu.twr
cpu.twx
cpu.tsi
cpu.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
cpu.ncd
cpu.par
cpu.pad
cpu_pad.txt
cpu_pad.csv
cpu.pad_txt
cpu.dly
reportgen.log
cpu.xpi
cpu.grf
cpu.itr
cpu_last_par.ncd
__projnav/par.log
cpu.placed_ncd_tracker
cpu.routed_ncd_tracker
cpu.cmd_log
PAR_NO_GUIDE_FILE_CPF "cpu"
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\cpu/_ngo
cpu.ngd
cpu_ngdbuild.nav
cpu.bld
Wcpu.ucf.untf
cpu.cmd_log
# Implementation : Map
cpu_map.ncd
cpu.ngm
cpu.pcf
cpu.nc1
cpu.mrp
cpu_map.mrp
cpu.mdf
__projnav/map.log
cpu.cmd_log
MAP_NO_GUIDE_FILE_CPF "cpu"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
cpu.twr
cpu.twx
cpu.tsi
cpu.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
cpu.ncd
cpu.par
cpu.pad
cpu_pad.txt
cpu_pad.csv
cpu.pad_txt
cpu.dly
reportgen.log
cpu.xpi
cpu.grf
cpu.itr
cpu_last_par.ncd
__projnav/par.log
cpu.placed_ncd_tracker
cpu.routed_ncd_tracker
cpu.cmd_log
PAR_NO_GUIDE_FILE_CPF "cpu"
# Generate Programming File
__projnav/cpu_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
cpu.ut
# Generate Programming File
cpu.bgn
cpu.rbt
cpu.ll
cpu.msk
cpu.drc
cpu.nky
cpu.bit
cpu.bin
cpu.isc
cpu.cmd_log
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana
cpu.stx
cpu.cmd_log
timer.ngc
getinstr.ngc
alu.ngc
exe.ngc
memcontrol.ngc
cpu.ngc
timer.ngr
getinstr.ngr
alu.ngr
exe.ngr
memcontrol.ngr
cpu.ngr
# XST (Creating Lso File) : 
cpu.lso
# xst flow : RunXST
cpu.syr
cpu.prj
cpu.sprj
cpu.ana