?? loadfw.rpt
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Project Information f:\dds2\dds\loadfw.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/21/2006 09:58:53
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
LOADFW
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
loadfw EPF10K10TC144-3 35 32 0 0 0 % 38 6 %
User Pins: 35 32 0
Device-Specific Information: f:\dds2\dds\loadfw.rpt
loadfw
***** Logic for device 'loadfw' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
F S S F
S S R Y Y R F F S
R R R R R R Y Y E R N N E R R R R Y R R R R R R R R R R R
E E E E E E N N Q E C C Q E E E E N E E E E E E E E E E E
S S S S S S C C W S F F W S G Q Q V S C S S S S S S S S S S S
E E E E E G E F F O V E R R O G E N W W F C E F E E E E E V E E E E E E
R R R R R N R R R R C R E E R N R D O O W C R R R R R R R C R R R R R R
V V V V V D V E E D C V Q Q D D V I R R W I V E V V V V V C V V V V V V
E E E E E I E Q Q 2 I E 2 2 1 I E N D D R N E Q E E E E E I E E E E E E
D D D D D O D 7 3 8 O D 6 4 1 O D T 1 2 N T D 1 D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
SYNCFREQ12 | 7 102 | FREQWORD6
SYNCFREQ15 | 8 101 | FREQWORD13
SYNCFREQ13 | 9 100 | SYNCFREQ4
SYNCFREQ11 | 10 99 | SYNCFREQ2
SYNCFREQ14 | 11 98 | SYNCFREQ6
SYNCFREQ10 | 12 97 | FREQWORD12
FREQWORD15 | 13 96 | FREQWORD10
SYNCFREQ9 | 14 95 | SYNCFREQ0
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
SYNCFREQ5 | 17 92 | FREQWORD31
FREQWORD3 | 18 91 | FREQWORD30
SYNCFREQ28 | 19 EPF10K10TC144-3 90 | SYNCFREQ30
SYNCFREQ8 | 20 89 | FREQWORD25
SYNCFREQ27 | 21 88 | FREQWORD8
SYNCFREQ25 | 22 87 | FREQWORD5
SYNCFREQ29 | 23 86 | FREQWORD7
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
SYNCFREQ16 | 26 83 | FREQWORD20
SYNCFREQ20 | 27 82 | FREQWORD18
SYNCFREQ18 | 28 81 | FREQWORD21
SYNCFREQ19 | 29 80 | FREQWORD17
SYNCFREQ22 | 30 79 | FREQWORD19
SYNCFREQ21 | 31 78 | FREQWORD23
SYNCFREQ23 | 32 77 | ^MSEL0
SYNCFREQ17 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
FREQWORD22 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
F R F G F F R R V F F S R G F V V R S F G G R R V R R R F G R R R R V R
R E R N R R E E C R R Y E N R C C E Y R N N E E C E E E R N E E E E C E
E S E D E E S S C E E N S D E C C S S E D D S S C S S S E D S S S S C S
Q E Q I Q Q E E I Q Q C E I Q I I E C Q I I E E I E E E Q I E E E E I E
W R W O W W R R O W W F R O W N N T L W N N R R O R R R W O R R R R O R
O V O O O V V O O R V O T T N K O T T V V V V V O V V V V V
R E R R R E E R R E E R R E E E E E R E E E E E
D D D D D D D D D Q D D D D D D D D D D D D D D
2 2 1 9 2 2 3 1 0 4
4 6 6 7 9 1 4
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\dds2\dds\loadfw.rpt
loadfw
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A10 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
A14 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 9/22( 40%)
B15 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
B19 6/ 8( 75%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
C21 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 61/96 ( 63%)
Total logic cells used: 38/576 ( 6%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.71/4 ( 92%)
Total fan-in: 141/2304 ( 6%)
Total input pins required: 35
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 38
Total flipflops required: 38
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 16/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 6 0 0 0 0 0 14/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 8/0
Total: 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 8 0 0 0 6 0 8 0 0 0 38/0
Device-Specific Information: f:\dds2\dds\loadfw.rpt
loadfw
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
56 - - - -- INPUT 0 0 0 1 FREQWORD0
126 - - - -- INPUT 0 0 0 1 FREQWORD1
125 - - - -- INPUT 0 0 0 1 FREQWORD2
18 - - B -- INPUT 0 0 0 1 FREQWORD3
65 - - - 09 INPUT 0 0 0 1 FREQWORD4
87 - - B -- INPUT 0 0 0 1 FREQWORD5
102 - - A -- INPUT 0 0 0 1 FREQWORD6
86 - - B -- INPUT 0 0 0 1 FREQWORD7
88 - - B -- INPUT 0 0 0 1 FREQWORD8
42 - - - 19 INPUT 0 0 0 1 FREQWORD9
96 - - A -- INPUT 0 0 0 1 FREQWORD10
130 - - - 14 INPUT 0 0 0 1 FREQWORD11
97 - - A -- INPUT 0 0 0 1 FREQWORD12
101 - - A -- INPUT 0 0 0 1 FREQWORD13
51 - - - 13 INPUT 0 0 0 1 FREQWORD14
13 - - A -- INPUT 0 0 0 1 FREQWORD15
41 - - - 20 INPUT 0 0 0 1 FREQWORD16
80 - - C -- INPUT 0 0 0 1 FREQWORD17
82 - - C -- INPUT 0 0 0 1 FREQWORD18
79 - - C -- INPUT 0 0 0 1 FREQWORD19
83 - - C -- INPUT 0 0 0 1 FREQWORD20
81 - - C -- INPUT 0 0 0 1 FREQWORD21
36 - - - 24 INPUT 0 0 0 1 FREQWORD22
78 - - C -- INPUT 0 0 0 1 FREQWORD23
37 - - - 23 INPUT 0 0 0 1 FREQWORD24
89 - - B -- INPUT 0 0 0 1 FREQWORD25
39 - - - 21 INPUT 0 0 0 1 FREQWORD26
46 - - - 17 INPUT 0 0 0 1 FREQWORD27
135 - - - 18 INPUT 0 0 0 1 FREQWORD28
47 - - - 16 INPUT 0 0 0 1 FREQWORD29
91 - - B -- INPUT 0 0 0 1 FREQWORD30
92 - - B -- INPUT 0 0 0 1 FREQWORD31
124 - - - -- INPUT 0 0 0 1 FWWRN
54 - - - -- INPUT 0 0 0 38 RESETN
55 - - - -- INPUT G 0 0 0 0 SYSCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dds2\dds\loadfw.rpt
loadfw
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
95 - - A -- OUTPUT 0 1 0 0 SYNCFREQ0
121 - - - 10 OUTPUT 0 1 0 0 SYNCFREQ1
99 - - A -- OUTPUT 0 1 0 0 SYNCFREQ2
136 - - - 19 OUTPUT 0 1 0 0 SYNCFREQ3
100 - - A -- OUTPUT 0 1 0 0 SYNCFREQ4
17 - - B -- OUTPUT 0 1 0 0 SYNCFREQ5
98 - - A -- OUTPUT 0 1 0 0 SYNCFREQ6
137 - - - 19 OUTPUT 0 1 0 0 SYNCFREQ7
20 - - B -- OUTPUT 0 1 0 0 SYNCFREQ8
14 - - A -- OUTPUT 0 1 0 0 SYNCFREQ9
12 - - A -- OUTPUT 0 1 0 0 SYNCFREQ10
10 - - A -- OUTPUT 0 1 0 0 SYNCFREQ11
7 - - A -- OUTPUT 0 1 0 0 SYNCFREQ12
9 - - A -- OUTPUT 0 1 0 0 SYNCFREQ13
11 - - A -- OUTPUT 0 1 0 0 SYNCFREQ14
8 - - A -- OUTPUT 0 1 0 0 SYNCFREQ15
26 - - C -- OUTPUT 0 1 0 0 SYNCFREQ16
33 - - C -- OUTPUT 0 1 0 0 SYNCFREQ17
28 - - C -- OUTPUT 0 1 0 0 SYNCFREQ18
29 - - C -- OUTPUT 0 1 0 0 SYNCFREQ19
27 - - C -- OUTPUT 0 1 0 0 SYNCFREQ20
31 - - C -- OUTPUT 0 1 0 0 SYNCFREQ21
30 - - C -- OUTPUT 0 1 0 0 SYNCFREQ22
32 - - C -- OUTPUT 0 1 0 0 SYNCFREQ23
131 - - - 15 OUTPUT 0 1 0 0 SYNCFREQ24
22 - - B -- OUTPUT 0 1 0 0 SYNCFREQ25
132 - - - 16 OUTPUT 0 1 0 0 SYNCFREQ26
21 - - B -- OUTPUT 0 1 0 0 SYNCFREQ27
19 - - B -- OUTPUT 0 1 0 0 SYNCFREQ28
23 - - B -- OUTPUT 0 1 0 0 SYNCFREQ29
90 - - B -- OUTPUT 0 1 0 0 SYNCFREQ30
48 - - - 15 OUTPUT 0 1 0 0 SYNCFREQ31
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