?? nco.rpt
字號:
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
A20 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A22 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
B13 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 6/22( 27%)
B14 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
B15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
B17 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
B20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
B21 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B22 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
C16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C19 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C20 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 7/8 ( 87%) 0/8 ( 0%) 7/8 ( 87%) 1/2 2/2 6/22( 27%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 50/53 ( 94%)
Total logic cells used: 161/576 ( 27%)
Total embedded cells used: 7/24 ( 29%)
Total EABs used: 1/3 ( 33%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 543/2304 ( 23%)
Total input pins required: 44
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 161
Total flipflops required: 116
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 7 8 0 0 4 0 0 0 1 7 1 8 0 1 0 8 0 3 0 8 1 8 82/7
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 8 0 8 0 0 8 8 8 0 0 55/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 8 0 0 0 0 24/0
Total: 8 8 8 7 8 0 0 4 0 0 0 1 7 9 15 8 9 8 8 8 19 8 16 1 8 161/7
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 1 FREQWORD0
42 - - - -- INPUT 0 0 0 1 FREQWORD1
84 - - - -- INPUT 0 0 0 1 FREQWORD2
43 - - - -- INPUT 0 0 0 1 FREQWORD3
21 - - B -- INPUT 0 0 0 1 FREQWORD4
52 - - - 19 INPUT 0 0 0 1 FREQWORD5
51 - - - 18 INPUT 0 0 0 1 FREQWORD6
64 - - B -- INPUT 0 0 0 1 FREQWORD7
67 - - B -- INPUT 0 0 0 1 FREQWORD8
48 - - - 15 INPUT 0 0 0 1 FREQWORD9
81 - - - 22 INPUT 0 0 0 1 FREQWORD10
65 - - B -- INPUT 0 0 0 1 FREQWORD11
66 - - B -- INPUT 0 0 0 1 FREQWORD12
25 - - B -- INPUT 0 0 0 1 FREQWORD13
24 - - B -- INPUT 0 0 0 1 FREQWORD14
22 - - B -- INPUT 0 0 0 1 FREQWORD15
62 - - C -- INPUT 0 0 0 1 FREQWORD16
58 - - C -- INPUT 0 0 0 1 FREQWORD17
28 - - C -- INPUT 0 0 0 1 FREQWORD18
29 - - C -- INPUT 0 0 0 1 FREQWORD19
60 - - C -- INPUT 0 0 0 1 FREQWORD20
80 - - - 23 INPUT 0 0 0 1 FREQWORD21
30 - - C -- INPUT 0 0 0 1 FREQWORD22
27 - - C -- INPUT 0 0 0 1 FREQWORD23
47 - - - 14 INPUT 0 0 0 1 FREQWORD24
49 - - - 16 INPUT 0 0 0 1 FREQWORD25
54 - - - 21 INPUT 0 0 0 1 FREQWORD26
37 - - - 09 INPUT 0 0 0 1 FREQWORD27
5 - - - 05 INPUT 0 0 0 1 FREQWORD28
10 - - - 01 INPUT 0 0 0 1 FREQWORD29
11 - - - 01 INPUT 0 0 0 1 FREQWORD30
7 - - - 03 INPUT 0 0 0 1 FREQWORD31
23 - - B -- INPUT 0 0 0 1 FWWRN
83 - - - 13 INPUT 0 0 0 1 PHASEWORD0
17 - - A -- INPUT 0 0 0 1 PHASEWORD1
9 - - - 02 INPUT 0 0 0 1 PHASEWORD2
73 - - A -- INPUT 0 0 0 1 PHASEWORD3
8 - - - 03 INPUT 0 0 0 1 PHASEWORD4
35 - - - 06 INPUT 0 0 0 1 PHASEWORD5
3 - - - 12 INPUT 0 0 0 1 PHASEWORD6
38 - - - 10 INPUT 0 0 0 1 PHASEWORD7
50 - - - 17 INPUT 0 0 0 1 PWWRN
2 - - - -- INPUT 0 0 0 116 RESETN
1 - - - -- INPUT G 0 0 0 0 SYSCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- OUTPUT 0 1 0 0 COS
6 - - - 04 OUTPUT 0 1 0 0 MCOS
18 - - A -- OUTPUT 0 1 0 0 MSIN
79 - - - 24 OUTPUT 0 1 0 0 NCOOUT0
78 - - - 24 OUTPUT 0 1 0 0 NCOOUT1
72 - - A -- OUTPUT 0 1 0 0 NCOOUT2
61 - - C -- OUTPUT 0 1 0 0 NCOOUT3
69 - - A -- OUTPUT 0 1 0 0 NCOOUT4
71 - - A -- OUTPUT 0 1 0 0 NCOOUT5
70 - - A -- OUTPUT 0 1 0 0 NCOOUT6
36 - - - 07 OUTPUT 0 1 0 0 NCOOUT7
16 - - A -- OUTPUT 0 1 0 0 SIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 14 DFFE + 2 0 0 2 |loadfw:U_loadfw|fwwrnm (|loadfw:U_loadfw|:100)
- 7 - B 14 DFFE + 1 1 0 1 |loadfw:U_loadfw|fwwrns (|loadfw:U_loadfw|:101)
- 1 - B 14 DFFE + 1 2 0 9 |loadfw:U_loadfw|loadp1 (|loadfw:U_loadfw|:102)
- 7 - B 13 DFFE + 1 1 0 9 |loadfw:U_loadfw|loadp2 (|loadfw:U_loadfw|:103)
- 5 - B 13 DFFE + 1 1 0 9 |loadfw:U_loadfw|loadp3 (|loadfw:U_loadfw|:104)
- 2 - A 20 DFFE + 1 1 0 8 |loadfw:U_loadfw|loadp4 (|loadfw:U_loadfw|:105)
- 5 - B 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw17 (|loadfw:U_loadfw|:106)
- 4 - B 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw16 (|loadfw:U_loadfw|:107)
- 2 - B 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw15 (|loadfw:U_loadfw|:108)
- 2 - B 14 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw14 (|loadfw:U_loadfw|:109)
- 6 - B 14 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw13 (|loadfw:U_loadfw|:110)
- 3 - B 22 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw12 (|loadfw:U_loadfw|:111)
- 1 - B 22 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw11 (|loadfw:U_loadfw|:112)
- 2 - B 13 DFFE + 2 1 0 3 |loadfw:U_loadfw|pipefw10 (|loadfw:U_loadfw|:113)
- 8 - B 17 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw27 (|loadfw:U_loadfw|:114)
- 8 - B 13 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw26 (|loadfw:U_loadfw|:115)
- 3 - B 13 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw25 (|loadfw:U_loadfw|:116)
- 1 - B 13 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw24 (|loadfw:U_loadfw|:117)
- 3 - B 21 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw23 (|loadfw:U_loadfw|:118)
- 1 - B 21 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw22 (|loadfw:U_loadfw|:119)
- 5 - B 15 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw21 (|loadfw:U_loadfw|:120)
- 4 - B 15 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw20 (|loadfw:U_loadfw|:121)
- 8 - C 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw37 (|loadfw:U_loadfw|:122)
- 2 - C 16 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw36 (|loadfw:U_loadfw|:123)
- 4 - A 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw35 (|loadfw:U_loadfw|:124)
- 6 - C 19 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw34 (|loadfw:U_loadfw|:125)
- 1 - C 16 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw33 (|loadfw:U_loadfw|:126)
- 1 - C 19 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw32 (|loadfw:U_loadfw|:127)
- 6 - C 16 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw31 (|loadfw:U_loadfw|:128)
- 5 - C 16 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw30 (|loadfw:U_loadfw|:129)
- 5 - A 05 DFFE + 2 1 0 1 |loadfw:U_loadfw|pipefw47 (|loadfw:U_loadfw|:130)
- 4 - A 05 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw46 (|loadfw:U_loadfw|:131)
- 3 - A 05 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw45 (|loadfw:U_loadfw|:132)
- 7 - A 01 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw44 (|loadfw:U_loadfw|:133)
- 3 - A 01 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw43 (|loadfw:U_loadfw|:134)
- 1 - A 20 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw42 (|loadfw:U_loadfw|:135)
- 5 - A 18 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw41 (|loadfw:U_loadfw|:136)
- 6 - A 18 DFFE + 2 1 0 2 |loadfw:U_loadfw|pipefw40 (|loadfw:U_loadfw|:137)
- 2 - A 14 DFFE + 2 0 0 2 |loadpw:U_loadpw|pwwrnm (|loadpw:U_loadpw|:28)
- 4 - A 14 DFFE + 1 1 0 1 |loadpw:U_loadpw|pwwrns (|loadpw:U_loadpw|:29)
- 6 - A 14 DFFE + 1 2 0 8 |loadpw:U_loadpw|load (|loadpw:U_loadpw|:30)
- 5 - A 02 DFFE + 2 1 0 1 |loadpw:U_loadpw|phswd7 (|loadpw:U_loadpw|:31)
- 3 - A 02 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd6 (|loadpw:U_loadpw|:32)
- 2 - A 02 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd5 (|loadpw:U_loadpw|:33)
- 3 - A 03 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd4 (|loadpw:U_loadpw|:34)
- 2 - A 03 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd3 (|loadpw:U_loadpw|:35)
- 6 - A 04 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd2 (|loadpw:U_loadpw|:36)
- 8 - A 14 DFFE + 2 1 0 2 |loadpw:U_loadpw|phswd1 (|loadpw:U_loadpw|:37)
- 3 - A 14 DFFE + 2 1 0 3 |loadpw:U_loadpw|phswd0 (|loadpw:U_loadpw|:38)
- 5 - B 22 OR2 0 4 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|pcarry1
- 7 - B 22 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|pcarry2
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