?? decoder.fit.rpt
字號:
Fitter report for decoder
Wed Sep 13 10:12:49 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. All Package Pins
11. I/O Standard
12. Dedicated Inputs I/O
13. Output Pin Default Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Macrocells
20. Logic Cell Interconnection
21. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Sep 13 10:12:49 2006 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; decoder ;
; Top-level Entity Name ; top ;
; Family ; MAX3000A ;
; Device ; EPM3032ATC44-10 ;
; Timing Models ; Final ;
; Total macrocells ; 8 / 32 ( 25 % ) ;
; Total pins ; 17 / 34 ( 50 % ) ;
+-----------------------+------------------------------------------+
+--------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------+--------------------+--------------------+
; Device ; EPM3032ATC44-10 ; ;
; Use smart compilation ; Off ; Off ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
+--------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/FPGA/work/decoder/decoder.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/FPGA/work/decoder/decoder.pin.
+--------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------+------------------+
; Resource ; Usage ;
+-------------------------------+------------------+
; Logic cells ; 8 / 32 ( 25 % ) ;
; Registers ; 8 / 32 ( 25 % ) ;
; Number of pterms used ; 16 ;
; User inserted logic elements ; 0 ;
; I/O pins ; 17 / 34 ( 50 % ) ;
; -- Clock pins ; 1 / 2 ( 50 % ) ;
; -- Dedicated input pins ; 1 / 2 ( 50 % ) ;
; Global signals ; 1 ;
; Shareable expanders ; 0 / 32 ( 0 % ) ;
; Parallel expanders ; 0 / 30 ( 0 % ) ;
; Cells using turbo bit ; 8 / 32 ( 25 % ) ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 48 ;
; Average fan-out ; 1.92 ;
+-------------------------------+------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+--------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; I/O Standard ; Location assigned by ;
+--------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
; clk ; 37 ; -- ; -- ; 8 ; 0 ; yes ; LVTTL ; User ;
; en ; 38 ; -- ; -- ; 8 ; 0 ; no ; LVTTL ; User ;
; sel[0] ; 2 ; -- ; 1 ; 8 ; 0 ; no ; LVTTL ; User ;
; sel[1] ; 3 ; -- ; 1 ; 8 ; 0 ; no ; LVTTL ; User ;
; sel[2] ; 5 ; -- ; 1 ; 8 ; 0 ; no ; LVTTL ; User ;
+--------+-------+----------+-----+-----------------------+--------------------+--------+--------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------------+
; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------------+
; Y[0] ; 12 ; -- ; 1 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[1] ; 13 ; -- ; 1 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[2] ; 14 ; -- ; 1 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[3] ; 15 ; -- ; 1 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[4] ; 18 ; -- ; 2 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[5] ; 19 ; -- ; 2 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[6] ; 20 ; -- ; 2 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
; Y[7] ; 21 ; -- ; 2 ; no ; no ; no ; no ; LVTTL ; User ; Unspecified ;
+------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------------+
+-------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; 1 ; 6 ; -- ; +TDI ; input ; LVTTL ; ; N ;
; 2 ; 7 ; -- ; sel[0] ; input ; LVTTL ; ; Y ;
; 3 ; 8 ; -- ; sel[1] ; input ; LVTTL ; ; Y ;
; 4 ; 9 ; -- ; GND ; gnd ; ; ; ;
; 5 ; 10 ; -- ; sel[2] ; input ; LVTTL ; ; Y ;
; 6 ; 11 ; -- ; RESERVED_INPUT ; ; ; ; ;
; 7 ; 12 ; -- ; +TMS ; input ; LVTTL ; ; N ;
; 8 ; 13 ; -- ; RESERVED_INPUT ; ; ; ; ;
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