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--B1_q0[0] is decoder:u0|q0[0]
--operation mode is normal

B1_q0[0]_lut_out = !B1L72 & !B1L13 & !B1L51 & !B1L21;
B1_q0[0] = DFFEAS(B1_q0[0]_lut_out, clk, VCC, , , , , , );


--B1_q0[1] is decoder:u0|q0[1]
--operation mode is normal

B1_q0[1]_lut_out = !B1L72 & !B1L13 & B1L63;
B1_q0[1] = DFFEAS(B1_q0[1]_lut_out, clk, VCC, , , , , , );


--B1_q0[2] is decoder:u0|q0[2]
--operation mode is normal

B1_q0[2]_lut_out = !B1L72 & !B1L13 & !B1L31;
B1_q0[2] = DFFEAS(B1_q0[2]_lut_out, clk, VCC, , , , , , );


--B1_q0[3] is decoder:u0|q0[3]
--operation mode is normal

B1_q0[3]_lut_out = !B1L51 & !B1L21 & !B1L23 & !B1L71;
B1_q0[3] = DFFEAS(B1_q0[3]_lut_out, clk, VCC, , , , , , );


--B1_q0[4] is decoder:u0|q0[4]
--operation mode is normal

B1_q0[4]_lut_out = B1L61 # B1L31 # B1L81 # B1L43;
B1_q0[4] = DFFEAS(B1_q0[4]_lut_out, clk, VCC, , , , , , );


--D1_q_a[0] is decoder:u0|altsyncram:reduce_or_rtl_0|altsyncram_a1j:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 2
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[0]_PORT_A_address = BUS(numh[0], numh[1], numh[2], numh[3], numh[4], numh[5], numh[6], numh[7], numh[8], numh[9]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = clk;
D1_q_a[0]_PORT_A_data_out = MEMORY(, , D1_q_a[0]_PORT_A_address_reg, , , , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out[0];


--B1_q0[6] is decoder:u0|q0[6]
--operation mode is normal

B1_q0[6]_lut_out = !B1L21 & !B1L23 & !B1L71 & !B1L43;
B1_q0[6] = DFFEAS(B1_q0[6]_lut_out, clk, VCC, , , , , , );


--B2_q0[0] is decoder:u1|q0[0]
--operation mode is normal

B2_q0[0]_lut_out = !B2L62 & !B2L03 & !B2L51 & !B2L21;
B2_q0[0] = DFFEAS(B2_q0[0]_lut_out, clk, VCC, , , , , , );


--B2_q0[1] is decoder:u1|q0[1]
--operation mode is normal

B2_q0[1]_lut_out = !B2L62 & !B2L03 & !B2L33 & !B2L61;
B2_q0[1] = DFFEAS(B2_q0[1]_lut_out, clk, VCC, , , , , , );


--B2_q0[2] is decoder:u1|q0[2]
--operation mode is normal

B2_q0[2]_lut_out = !B2L62 & !B2L03 & !B2L31;
B2_q0[2] = DFFEAS(B2_q0[2]_lut_out, clk, VCC, , , , , , );


--B2_q0[3] is decoder:u1|q0[3]
--operation mode is normal

B2_q0[3]_lut_out = !B2L51 & !B2L21 & !B2L13 & !B2L71;
B2_q0[3] = DFFEAS(B2_q0[3]_lut_out, clk, VCC, , , , , , );


--B2_q0[4] is decoder:u1|q0[4]
--operation mode is normal

B2_q0[4]_lut_out = B2L61 # B2L31 # B2L81 # B2L53;
B2_q0[4] = DFFEAS(B2_q0[4]_lut_out, clk, VCC, , , , , , );


--E1_q_a[0] is decoder:u1|altsyncram:reduce_or_rtl_1|altsyncram_b1j:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 2
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(numt[0], numt[1], numt[2], numt[3], numt[4], numt[5], numt[6], numt[7], numt[8], numt[9]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = clk;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--B2_q0[6] is decoder:u1|q0[6]
--operation mode is normal

B2_q0[6]_lut_out = !B2L21 & !B2L13 & !B2L71 & !B2L53;
B2_q0[6] = DFFEAS(B2_q0[6]_lut_out, clk, VCC, , , , , , );


--B3_q0[0] is decoder:u2|q0[0]
--operation mode is normal

B3_q0[0]_lut_out = !B3L62 & !B3L03 & !B3L51 & !B3L21;
B3_q0[0] = DFFEAS(B3_q0[0]_lut_out, clk, VCC, , , , , , );


--B3_q0[1] is decoder:u2|q0[1]
--operation mode is normal

B3_q0[1]_lut_out = !B3L62 & !B3L03 & !B3L33 & !B3L61;
B3_q0[1] = DFFEAS(B3_q0[1]_lut_out, clk, VCC, , , , , , );


--B3_q0[2] is decoder:u2|q0[2]
--operation mode is normal

B3_q0[2]_lut_out = !B3L62 & !B3L03 & !B3L31;
B3_q0[2] = DFFEAS(B3_q0[2]_lut_out, clk, VCC, , , , , , );


--B3_q0[3] is decoder:u2|q0[3]
--operation mode is normal

B3_q0[3]_lut_out = !B3L51 & !B3L21 & !B3L13 & !B3L71;
B3_q0[3] = DFFEAS(B3_q0[3]_lut_out, clk, VCC, , , , , , );


--B3_q0[4] is decoder:u2|q0[4]
--operation mode is normal

B3_q0[4]_lut_out = B3L61 # B3L31 # B3L81 # B3L53;
B3_q0[4] = DFFEAS(B3_q0[4]_lut_out, clk, VCC, , , , , , );


--F1_q_a[0] is decoder:u2|altsyncram:reduce_or_rtl_2|altsyncram_c1j:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 2
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[0]_PORT_A_address = BUS(numo[0], numo[1], numo[2], numo[3], numo[4], numo[5], numo[6], numo[7], numo[8], numo[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = clk;
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0] = F1_q_a[0]_PORT_A_data_out[0];


--B3_q0[6] is decoder:u2|q0[6]
--operation mode is normal

B3_q0[6]_lut_out = !B3L21 & !B3L13 & !B3L71 & !B3L53;
B3_q0[6] = DFFEAS(B3_q0[6]_lut_out, clk, VCC, , , , , , );


--A1L43Q is lockopen~reg0
--operation mode is normal

A1L43Q_lut_out = !A1L27 & !A1L37 & !A1L47;
A1L43Q = DFFEAS(A1L43Q_lut_out, clk, VCC, , enable1, , , , );


--B1L91 is decoder:u0|reduce_nor~1826
--operation mode is normal

B1L91 = !numh[8] & !numh[9];


--B1L02 is decoder:u0|reduce_nor~1827
--operation mode is normal

B1L02 = B1L91 & !numh[0] & !numh[7] & !numh[6];


--B1L12 is decoder:u0|reduce_nor~1828
--operation mode is normal

B1L12 = !numh[1] & !numh[2] & !numh[3];


--B1L51 is decoder:u0|reduce_nor~4
--operation mode is normal

B1L51 = B1L02 & B1L12 & numh[4] & !numh[5];


--B1L22 is decoder:u0|reduce_nor~1829
--operation mode is normal

B1L22 = !numh[7] & !numh[8] & !numh[9] & !numh[6];


--B1L32 is decoder:u0|reduce_nor~1830
--operation mode is normal

B1L32 = B1L22 & !numh[5] & !numh[0] & !numh[4];


--B1L21 is decoder:u0|reduce_nor~1
--operation mode is normal

B1L21 = numh[1] & B1L32 & !numh[2] & !numh[3];


--B1L42 is decoder:u0|reduce_nor~1831
--operation mode is normal

B1L42 = numh[8] $ numh[9];


--B1L52 is decoder:u0|reduce_nor~1832
--operation mode is normal

B1L52 = numh[0] & !numh[1] & !numh[2] & !numh[3] # !numh[0] & (numh[1] & !numh[2] & !numh[3] # !numh[1] & (numh[2] $ numh[3]));


--B1L62 is decoder:u0|reduce_nor~1833
--operation mode is normal

B1L62 = numh[4] & (!numh[5] & B1L53) # !numh[4] & (numh[5] & (B1L53) # !numh[5] & B1L52);


--B1L72 is decoder:u0|reduce_nor~1834
--operation mode is normal

B1L72 = !B1L42 & (numh[7] & numh[6] # !numh[7] & !numh[6] & !B1L62);


--B1L82 is decoder:u0|reduce_nor~1835
--operation mode is normal

B1L82 = B1L12 & !numh[5] & !numh[0] & !numh[4];


--B1L92 is decoder:u0|reduce_nor~1836
--operation mode is normal

B1L92 = B1L82 & (!numh[7] & !numh[6]);


--B1L03 is decoder:u0|reduce_nor~1837
--operation mode is normal

B1L03 = !B1L82 & (numh[7] $ numh[6]);


--B1L13 is decoder:u0|reduce_nor~1838
--operation mode is normal

B1L13 = numh[8] & (numh[9] # !B1L92) # !numh[8] & (numh[9] & !B1L92 # !numh[9] & (B1L03));


--B1L23 is decoder:u0|reduce_nor~1839
--operation mode is normal

B1L23 = B1L72 # B1L13;


--B1L33 is decoder:u0|reduce_nor~1840
--operation mode is normal

B1L33 = !numh[1] & !numh[2] & !numh[3] & !numh[4];


--B1L61 is decoder:u0|reduce_nor~6
--operation mode is normal

B1L61 = B1L91 & numh[6] & B1L82 & !numh[7];


--B1L63 is decoder:u0|reduce_or~157
--operation mode is normal

B1L63 = !B1L61 & (!B1L33 # !B1L02 # !numh[5]);


--B1L31 is decoder:u0|reduce_nor~2
--operation mode is normal

B1L31 = numh[2] & B1L32 & !numh[1] & !numh[3];


--B1L71 is decoder:u0|reduce_nor~7
--operation mode is normal

B1L71 = numh[7] & B1L91 & B1L82 & !numh[6];


--B1L81 is decoder:u0|reduce_nor~8
--operation mode is normal

B1L81 = numh[8] & B1L92 & (!numh[9]);


--B1L43 is decoder:u0|reduce_nor~1841
--operation mode is normal

B1L43 = numh[0] & B1L22 & B1L33 & !numh[5];


--B2L91 is decoder:u1|reduce_nor~1769
--operation mode is normal

B2L91 = !numt[7] & !numt[8] & !numt[9] & !numt[6];


--B2L02 is decoder:u1|reduce_nor~1770
--operation mode is normal

B2L02 = B2L91 & (!numt[0]);


--B2L12 is decoder:u1|reduce_nor~1771
--operation mode is normal

B2L12 = !numt[1] & !numt[2] & !numt[3];


--B2L51 is decoder:u1|reduce_nor~4
--operation mode is normal

B2L51 = B2L02 & B2L12 & numt[4] & !numt[5];


--B2L22 is decoder:u1|reduce_nor~1772
--operation mode is normal

B2L22 = B2L91 & !numt[5] & !numt[0] & !numt[4];


--B2L21 is decoder:u1|reduce_nor~1
--operation mode is normal

B2L21 = numt[1] & B2L22 & !numt[2] & !numt[3];


--B2L32 is decoder:u1|reduce_nor~1773
--operation mode is normal

B2L32 = numt[8] $ numt[9];


--B2L42 is decoder:u1|reduce_nor~1774
--operation mode is normal

B2L42 = numt[0] & !numt[1] & !numt[2] & !numt[3] # !numt[0] & (numt[1] & !numt[2] & !numt[3] # !numt[1] & (numt[2] $ numt[3]));


--B2L52 is decoder:u1|reduce_nor~1775
--operation mode is normal

B2L52 = numt[4] & (!numt[5] & B2L63) # !numt[4] & (numt[5] & (B2L63) # !numt[5] & B2L42);


--B2L62 is decoder:u1|reduce_nor~1776
--operation mode is normal

B2L62 = !B2L32 & (numt[7] & numt[6] # !numt[7] & !numt[6] & !B2L52);


--B2L72 is decoder:u1|reduce_nor~1777
--operation mode is normal

B2L72 = B2L12 & !numt[5] & !numt[0] & !numt[4];


--B2L82 is decoder:u1|reduce_nor~1778
--operation mode is normal

B2L82 = B2L72 & (!numt[7] & !numt[6]);


--B2L92 is decoder:u1|reduce_nor~1779
--operation mode is normal

B2L92 = !B2L72 & (numt[7] $ numt[6]);


--B2L03 is decoder:u1|reduce_nor~1780
--operation mode is normal

B2L03 = numt[8] & (numt[9] # !B2L82) # !numt[8] & (numt[9] & !B2L82 # !numt[9] & (B2L92));


--B2L13 is decoder:u1|reduce_nor~1781
--operation mode is normal

B2L13 = B2L62 # B2L03;


--B2L23 is decoder:u1|reduce_nor~1782
--operation mode is normal

B2L23 = !numt[1] & !numt[2] & !numt[3] & !numt[4];


--B2L33 is decoder:u1|reduce_nor~1783
--operation mode is normal

B2L33 = numt[5] & B2L91 & B2L23 & !numt[0];


--B2L43 is decoder:u1|reduce_nor~1784
--operation mode is normal

B2L43 = !numt[8] & !numt[9];


--B2L61 is decoder:u1|reduce_nor~6
--operation mode is normal

B2L61 = B2L43 & numt[6] & B2L72 & !numt[7];


--B2L31 is decoder:u1|reduce_nor~2
--operation mode is normal

B2L31 = numt[2] & B2L22 & !numt[1] & !numt[3];


--B2L71 is decoder:u1|reduce_nor~7
--operation mode is normal

B2L71 = numt[7] & B2L43 & B2L72 & !numt[6];


--B2L81 is decoder:u1|reduce_nor~8
--operation mode is normal

B2L81 = numt[8] & B2L82 & (!numt[9]);


--B2L53 is decoder:u1|reduce_nor~1785
--operation mode is normal

B2L53 = numt[0] & B2L91 & B2L23 & !numt[5];


--B3L91 is decoder:u2|reduce_nor~1769
--operation mode is normal

B3L91 = !numo[7] & !numo[8] & !numo[9] & !numo[6];


--B3L02 is decoder:u2|reduce_nor~1770
--operation mode is normal

B3L02 = numo[4] & !numo[1] & !numo[2] & !numo[3];


--B3L51 is decoder:u2|reduce_nor~4
--operation mode is normal

B3L51 = B3L91 & B3L02 & !numo[5] & !numo[0];


--B3L12 is decoder:u2|reduce_nor~1771
--operation mode is normal

B3L12 = B3L91 & !numo[5] & !numo[0] & !numo[4];


--B3L21 is decoder:u2|reduce_nor~1
--operation mode is normal

B3L21 = numo[1] & B3L12 & !numo[2] & !numo[3];


--B3L22 is decoder:u2|reduce_nor~1772
--operation mode is normal

B3L22 = numo[8] $ numo[9];


--B3L32 is decoder:u2|reduce_nor~1773
--operation mode is normal

B3L32 = numo[0] & !numo[1] & !numo[2] & !numo[3] # !numo[0] & (numo[1] & !numo[2] & !numo[3] # !numo[1] & (numo[2] $ numo[3]));


--B3L42 is decoder:u2|reduce_nor~1774
--operation mode is normal

B3L42 = !numo[1] & !numo[2] & !numo[3];


--B3L52 is decoder:u2|reduce_nor~1775
--operation mode is normal

B3L52 = numo[4] & (!numo[5] & B3L63) # !numo[4] & (numo[5] & (B3L63) # !numo[5] & B3L32);


--B3L62 is decoder:u2|reduce_nor~1776
--operation mode is normal

B3L62 = !B3L22 & (numo[7] & numo[6] # !numo[7] & !numo[6] & !B3L52);


--B3L72 is decoder:u2|reduce_nor~1777
--operation mode is normal

B3L72 = B3L42 & !numo[5] & !numo[0] & !numo[4];


--B3L82 is decoder:u2|reduce_nor~1778
--operation mode is normal

B3L82 = B3L72 & (!numo[7] & !numo[6]);


--B3L92 is decoder:u2|reduce_nor~1779
--operation mode is normal

B3L92 = !B3L72 & (numo[7] $ numo[6]);


--B3L03 is decoder:u2|reduce_nor~1780
--operation mode is normal

B3L03 = numo[8] & (numo[9] # !B3L82) # !numo[8] & (numo[9] & !B3L82 # !numo[9] & (B3L92));


--B3L13 is decoder:u2|reduce_nor~1781
--operation mode is normal

B3L13 = B3L62 # B3L03;


--B3L23 is decoder:u2|reduce_nor~1782
--operation mode is normal

B3L23 = !numo[1] & !numo[2] & !numo[3] & !numo[4];


--B3L33 is decoder:u2|reduce_nor~1783
--operation mode is normal

B3L33 = numo[5] & B3L91 & B3L23 & !numo[0];


--B3L43 is decoder:u2|reduce_nor~1784
--operation mode is normal

B3L43 = !numo[8] & !numo[9];


--B3L61 is decoder:u2|reduce_nor~6
--operation mode is normal

B3L61 = B3L43 & numo[6] & B3L72 & !numo[7];


--B3L31 is decoder:u2|reduce_nor~2
--operation mode is normal

B3L31 = numo[2] & B3L12 & !numo[1] & !numo[3];


--B3L71 is decoder:u2|reduce_nor~7
--operation mode is normal

B3L71 = numo[7] & B3L43 & B3L72 & !numo[6];


--B3L81 is decoder:u2|reduce_nor~8
--operation mode is normal

B3L81 = numo[8] & B3L82 & (!numo[9]);


--B3L53 is decoder:u2|reduce_nor~1785
--operation mode is normal

B3L53 = numo[0] & B3L91 & B3L23 & !numo[5];


--tempo[0] is tempo[0]
--operation mode is normal

tempo[0]_lut_out = F1_q_a[1];
tempo[0] = DFFEAS(tempo[0]_lut_out, clk, VCC, , enable0, , , , );


--F1_q_a[1] is decoder:u2|altsyncram:reduce_or_rtl_2|altsyncram_c1j:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 2
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[1]_PORT_A_address = BUS(numo[0], numo[1], numo[2], numo[3], numo[4], numo[5], numo[6], numo[7], numo[8], numo[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = clk;
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );