library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is 
port(clk: in std_logic;
     data: in std_logic_vector(9 downto 0);
     q0: out std_logic_vector(7 downto 0);
     q1: out std_logic_vector(3 downto 0));
end entity;
architecture arch of decoder is
begin 
process(clk,data)
begin 
if clk'event and clk='1' then 
   case data is
     when "0000000001"=>q0<="00111111";q1<="0000";
     when "0000000010"=>q0<="00000110";q1<="0001";
     when "0000000100"=>q0<="01011011";q1<="0010";
     when "0000001000"=>q0<="01001111";q1<="0011";
     when "0000010000"=>q0<="01100110";q1<="0100";
     when "0000100000"=>q0<="01101101";q1<="0101";
     when "0001000000"=>q0<="01111101";q1<="0110";
     when "0010000000"=>q0<="00000111";q1<="0111";
     when "0100000000"=>q0<="01111111";q1<="1000";
     when "1000000000"=>q0<="01101111";q1<="1001";
     when others=>q0<="00000000";q1<="0000";
   end case;
end if;
end process;
end arch;