library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  hen is

port(
    
    seg1:   in std_logic_vector(7 downto 0);
    seg2 :  in std_logic_vector(7 downto 0);
     seg1out:   out std_logic_vector(7 downto 0);
    seg2out :  out std_logic_vector(7 downto 0)
   
);
end hen;

 architecture a of hen is
   begin 
  seg1out<=seg1;
  seg2out<=seg2;

end a;