?? hen.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hen is
port(
seg1: in std_logic_vector(7 downto 0);
seg2 : in std_logic_vector(7 downto 0);
seg1out: out std_logic_vector(7 downto 0);
seg2out : out std_logic_vector(7 downto 0)
);
end hen;
architecture a of hen is
begin
seg1out<=seg1;
seg2out<=seg2;
end a;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -