//Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
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//agreement for further details.

// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module freedev_vga_inst (
                          // inputs:
                           clk,
                           m_readdata,
                           m_readdatavalid,
                           m_waitrequest,
                           pclk,
                           rst_n,
                           s_address,
                           s_chipselect_n,
                           s_read_n,
                           s_write_n,
                           s_writedata,

                          // outputs:
                           b,
                           blank,
                           g,
                           hsync,
                           m_address,
                           m_burstcount,
                           m_byteenable,
                           m_read,
                           m_write,
                           m_writedata,
                           psave,
                           r,
                           s_irq,
                           s_readdata,
                           sync,
                           vsync
                        )
;

  output  [  7: 0] b;
  output           blank;
  output  [  7: 0] g;
  output           hsync;
  output  [ 31: 0] m_address;
  output  [  7: 0] m_burstcount;
  output  [  3: 0] m_byteenable;
  output           m_read;
  output           m_write;
  output  [ 31: 0] m_writedata;
  output           psave;
  output  [  7: 0] r;
  output           s_irq;
  output  [ 31: 0] s_readdata;
  output           sync;
  output           vsync;
  input            clk;
  input   [ 31: 0] m_readdata;
  input            m_readdatavalid;
  input            m_waitrequest;
  input            pclk;
  input            rst_n;
  input   [  3: 0] s_address;
  input            s_chipselect_n;
  input            s_read_n;
  input            s_write_n;
  input   [ 31: 0] s_writedata;

  wire    [  7: 0] b;
  wire             blank;
  wire    [  7: 0] g;
  wire             hsync;
  wire    [ 31: 0] m_address;
  wire    [  7: 0] m_burstcount;
  wire    [  3: 0] m_byteenable;
  wire             m_read;
  wire             m_write;
  wire    [ 31: 0] m_writedata;
  wire             psave;
  wire    [  7: 0] r;
  wire             s_irq;
  wire    [ 31: 0] s_readdata;
  wire             sync;
  wire             vsync;
  freedev_vga the_freedev_vga
    (
      .b               (b),
      .blank           (blank),
      .clk             (clk),
      .g               (g),
      .hsync           (hsync),
      .m_address       (m_address),
      .m_burstcount    (m_burstcount),
      .m_byteenable    (m_byteenable),
      .m_read          (m_read),
      .m_readdata      (m_readdata),
      .m_readdatavalid (m_readdatavalid),
      .m_waitrequest   (m_waitrequest),
      .m_write         (m_write),
      .m_writedata     (m_writedata),
      .pclk            (pclk),
      .psave           (psave),
      .r               (r),
      .rst_n           (rst_n),
      .s_address       (s_address),
      .s_chipselect_n  (s_chipselect_n),
      .s_irq           (s_irq),
      .s_read_n        (s_read_n),
      .s_readdata      (s_readdata),
      .s_write_n       (s_write_n),
      .s_writedata     (s_writedata),
      .sync            (sync),
      .vsync           (vsync)
    );
  defparam the_freedev_vga.IDLE = 1,
           the_freedev_vga.R_DATA = 8,
           the_freedev_vga.R_START0 = 2,
           the_freedev_vga.R_START1 = 4;


endmodule