//asmi_asmi_control_port_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign asmi_asmi_control_port_arbitration_holdoff_internal = asmi_asmi_control_port_begins_xfer & asmi_asmi_control_port_firsttransfer;

  //~asmi_asmi_control_port_read_n assignment, which is an e_mux
  assign asmi_asmi_control_port_read_n = ~(cpu_0_data_master_granted_asmi_asmi_control_port & cpu_0_data_master_read);

  //~asmi_asmi_control_port_write_n assignment, which is an e_mux
  assign asmi_asmi_control_port_write_n = ~(cpu_0_data_master_granted_asmi_asmi_control_port & cpu_0_data_master_write);

  //asmi_asmi_control_port_address mux, which is an e_mux
  assign asmi_asmi_control_port_address = cpu_0_data_master_address_to_slave >> 2;

  //d1_asmi_asmi_control_port_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_asmi_asmi_control_port_end_xfer <= 1;
      else if (1)
          d1_asmi_asmi_control_port_end_xfer <= asmi_asmi_control_port_end_xfer;
    end


  //asmi_asmi_control_port_waits_for_read in a cycle, which is an e_mux
  assign asmi_asmi_control_port_waits_for_read = asmi_asmi_control_port_in_a_read_cycle & asmi_asmi_control_port_begins_xfer;

  //asmi_asmi_control_port_in_a_read_cycle assignment, which is an e_assign
  assign asmi_asmi_control_port_in_a_read_cycle = cpu_0_data_master_granted_asmi_asmi_control_port & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = asmi_asmi_control_port_in_a_read_cycle;

  //asmi_asmi_control_port_waits_for_write in a cycle, which is an e_mux
  assign asmi_asmi_control_port_waits_for_write = asmi_asmi_control_port_in_a_write_cycle & asmi_asmi_control_port_begins_xfer;

  //asmi_asmi_control_port_in_a_write_cycle assignment, which is an e_assign
  assign asmi_asmi_control_port_in_a_write_cycle = cpu_0_data_master_granted_asmi_asmi_control_port & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = asmi_asmi_control_port_in_a_write_cycle;

  assign wait_for_asmi_asmi_control_port_counter = 0;
  //assign asmi_asmi_control_port_irq_from_sa = asmi_asmi_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign asmi_asmi_control_port_irq_from_sa = asmi_asmi_control_port_irq;


  // synthesis attribute asmi_asmi_control_port_arbitrator auto_dissolve FALSE

endmodule


module cpu_0_data_master_arbitrator (
                                      // inputs:
                                       asmi_asmi_control_port_irq_from_sa,
                                       asmi_asmi_control_port_readdata_from_sa,
                                       cfi_flash_0_s1_wait_counter_eq_0,
                                       cfi_flash_0_s1_wait_counter_eq_1,
                                       clk,
                                       cpu_0_data_master_address,
                                       cpu_0_data_master_byteenable_cfi_flash_0_s1,
                                       cpu_0_data_master_byteenable_payload_buffer_s1,
                                       cpu_0_data_master_granted_asmi_asmi_control_port,
                                       cpu_0_data_master_granted_cfi_flash_0_s1,
                                       cpu_0_data_master_granted_data_RAM_s1,
                                       cpu_0_data_master_granted_firmware_ROM_s1,
                                       cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_granted_payload_buffer_s1,
                                       cpu_0_data_master_granted_sysid_control_slave,
                                       cpu_0_data_master_qualified_request_asmi_asmi_control_port,
                                       cpu_0_data_master_qualified_request_cfi_flash_0_s1,
                                       cpu_0_data_master_qualified_request_data_RAM_s1,
                                       cpu_0_data_master_qualified_request_firmware_ROM_s1,
                                       cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_qualified_request_payload_buffer_s1,
                                       cpu_0_data_master_qualified_request_sysid_control_slave,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_asmi_asmi_control_port,
                                       cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
                                       cpu_0_data_master_read_data_valid_data_RAM_s1,
                                       cpu_0_data_master_read_data_valid_firmware_ROM_s1,
                                       cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_read_data_valid_payload_buffer_s1,
                                       cpu_0_data_master_read_data_valid_sysid_control_slave,
                                       cpu_0_data_master_requests_asmi_asmi_control_port,
                                       cpu_0_data_master_requests_cfi_flash_0_s1,
                                       cpu_0_data_master_requests_data_RAM_s1,
                                       cpu_0_data_master_requests_firmware_ROM_s1,
                                       cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
                                       cpu_0_data_master_requests_payload_buffer_s1,
                                       cpu_0_data_master_requests_sysid_control_slave,
                                       cpu_0_data_master_write,
                                       cpu_0_data_master_writedata,
                                       d1_asmi_asmi_control_port_end_xfer,
                                       d1_data_RAM_s1_end_xfer,
                                       d1_firmware_ROM_s1_end_xfer,
                                       d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
                                       d1_payload_buffer_s1_end_xfer,
                                       d1_sysid_control_slave_end_xfer,
                                       d1_tri_state_bridge_0_avalon_slave_end_xfer,
                                       data_RAM_s1_readdata_from_sa,
                                       firmware_ROM_s1_readdata_from_sa,
                                       incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
                                       jtag_uart_0_avalon_jtag_slave_irq_from_sa,
                                       jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
                                       jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
                                       payload_buffer_s1_readdata_from_sa,
                                       registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
                                       registered_cpu_0_data_master_read_data_valid_data_RAM_s1,
                                       registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1,
                                       registered_cpu_0_data_master_read_data_valid_payload_buffer_s1,
                                       reset_n,
                                       sysid_control_slave_readdata_from_sa,

                                      // outputs:
                                       cpu_0_data_master_address_to_slave,
                                       cpu_0_data_master_dbs_address,
                                       cpu_0_data_master_dbs_write_16,
                                       cpu_0_data_master_irq,
                                       cpu_0_data_master_no_byte_enables_and_last_term,
                                       cpu_0_data_master_readdata,
                                       cpu_0_data_master_reset_n,
                                       cpu_0_data_master_waitrequest
                                    );

  output  [ 27: 0] cpu_0_data_master_address_to_slave;
  output  [  1: 0] cpu_0_data_master_dbs_address;
  output  [ 15: 0] cpu_0_data_master_dbs_write_16;
  output  [ 31: 0] cpu_0_data_master_irq;
  output           cpu_0_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_0_data_master_readdata;
  output           cpu_0_data_master_reset_n;
  output           cpu_0_data_master_waitrequest;
  input            asmi_asmi_control_port_irq_from_sa;
  input   [ 15: 0] asmi_asmi_control_port_readdata_from_sa;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            cfi_flash_0_s1_wait_counter_eq_1;
  input            clk;
  input   [ 27: 0] cpu_0_data_master_address;
  input   [  1: 0] cpu_0_data_master_byteenable_cfi_flash_0_s1;
  input   [  1: 0] cpu_0_data_master_byteenable_payload_buffer_s1;
  input            cpu_0_data_master_granted_asmi_asmi_control_port;
  input            cpu_0_data_master_granted_cfi_flash_0_s1;
  input            cpu_0_data_master_granted_data_RAM_s1;
  input            cpu_0_data_master_granted_firmware_ROM_s1;
  input            cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_granted_payload_buffer_s1;
  input            cpu_0_data_master_granted_sysid_control_slave;
  input            cpu_0_data_master_qualified_request_asmi_asmi_control_port;
  input            cpu_0_data_master_qualified_request_cfi_flash_0_s1;
  input            cpu_0_data_master_qualified_request_data_RAM_s1;
  input            cpu_0_data_master_qualified_request_firmware_ROM_s1;
  input            cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_qualified_request_payload_buffer_s1;
  input            cpu_0_data_master_qualified_request_sysid_control_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_asmi_asmi_control_port;
  input            cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
  input            cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  input            cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_read_data_valid_payload_buffer_s1;
  input            cpu_0_data_master_read_data_valid_sysid_control_slave;
  input            cpu_0_data_master_requests_asmi_asmi_control_port;
  input            cpu_0_data_master_requests_cfi_flash_0_s1;
  input            cpu_0_data_master_requests_data_RAM_s1;
  input            cpu_0_data_master_requests_firmware_ROM_s1;
  input            cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
  input            cpu_0_data_master_requests_payload_buffer_s1;
  input            cpu_0_data_master_requests_sysid_control_slave;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            d1_asmi_asmi_control_port_end_xfer;
  input            d1_data_RAM_s1_end_xfer;
  input            d1_firmware_ROM_s1_end_xfer;
  input            d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
  input            d1_payload_buffer_s1_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input   [ 31: 0] data_RAM_s1_readdata_from_sa;
  input   [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  input   [ 15: 0] incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;
  input            jtag_uart_0_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  input   [ 15: 0] payload_buffer_s1_readdata_from_sa;
  input            registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
  input            registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1;
  input            registered_cpu_0_data_master_read_data_valid_payload_buffer_s1;
  input            reset_n;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;

  wire    [ 27: 0] cpu_0_data_master_address_to_slave;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_0_data_master_irq;
  reg              cpu_0_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_reset_n;
  wire             cpu_0_data_master_run;
  reg              cpu_0_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_0_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  reg     [ 31: 0] registered_cpu_0_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~cpu_0_data_master_qualified_request_asmi_asmi_control_port | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_asmi_asmi_control_port | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_data_RAM_s1 | registered_cpu_0_data_master_read_data_valid_data_RAM_s1 | ~cpu_0_data_master_requests_data_RAM_s1) & (cpu_0_data_master_granted_data_RAM_s1 | ~cpu_0_data_master_qualified_request_data_RAM_s1) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_data_RAM_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_firmware_ROM_s1 | registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 | ~cpu_0_data_master_requests_firmware_ROM_s1) & (cpu_0_data_master_granted_firmware_ROM_s1 | ~cpu_0_data_master_qualified_request_firmware_ROM_s1) & ((~cpu_0_data_master_qualified_request_firmware_ROM_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_firmware_ROM_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_read | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_write | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_payload_buffer_s1 | (registered_cpu_0_data_master_read_data_valid_payload_buffer_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_payload_buffer_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_payload_buffer_s1) & (cpu_0_data_master_granted_payload_buffer_s1 | ~cpu_0_data_master_qualified_request_payload_buffer_s1);

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_data_master_run = r_0 & r_1;