// outputs:
                                              cpu_0_instruction_master_address_to_slave,
                                              cpu_0_instruction_master_dbs_address,
                                              cpu_0_instruction_master_readdata,
                                              cpu_0_instruction_master_waitrequest
                                           );

  output  [ 27: 0] cpu_0_instruction_master_address_to_slave;
  output  [  1: 0] cpu_0_instruction_master_dbs_address;
  output  [ 31: 0] cpu_0_instruction_master_readdata;
  output           cpu_0_instruction_master_waitrequest;
  input            cfi_flash_0_s1_wait_counter_eq_0;
  input            cfi_flash_0_s1_wait_counter_eq_1;
  input            clk;
  input   [ 27: 0] cpu_0_instruction_master_address;
  input            cpu_0_instruction_master_granted_cfi_flash_0_s1;
  input            cpu_0_instruction_master_granted_data_RAM_s1;
  input            cpu_0_instruction_master_granted_firmware_ROM_s1;
  input            cpu_0_instruction_master_granted_payload_buffer_s1;
  input            cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
  input            cpu_0_instruction_master_qualified_request_data_RAM_s1;
  input            cpu_0_instruction_master_qualified_request_firmware_ROM_s1;
  input            cpu_0_instruction_master_qualified_request_payload_buffer_s1;
  input            cpu_0_instruction_master_read;
  input            cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
  input            cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  input            cpu_0_instruction_master_read_data_valid_firmware_ROM_s1;
  input            cpu_0_instruction_master_read_data_valid_payload_buffer_s1;
  input            cpu_0_instruction_master_requests_cfi_flash_0_s1;
  input            cpu_0_instruction_master_requests_data_RAM_s1;
  input            cpu_0_instruction_master_requests_firmware_ROM_s1;
  input            cpu_0_instruction_master_requests_payload_buffer_s1;
  input            d1_data_RAM_s1_end_xfer;
  input            d1_firmware_ROM_s1_end_xfer;
  input            d1_payload_buffer_s1_end_xfer;
  input            d1_tri_state_bridge_0_avalon_slave_end_xfer;
  input   [ 31: 0] data_RAM_s1_readdata_from_sa;
  input   [ 31: 0] firmware_ROM_s1_readdata_from_sa;
  input   [ 15: 0] incoming_tri_state_bridge_0_data;
  input   [ 15: 0] payload_buffer_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [ 27: 0] cpu_0_instruction_master_address_last_time;
  wire    [ 27: 0] cpu_0_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_0_instruction_master_dbs_address;
  wire    [  1: 0] cpu_0_instruction_master_dbs_increment;
  reg              cpu_0_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_0_instruction_master_readdata;
  wire             cpu_0_instruction_master_run;
  wire             cpu_0_instruction_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_data_RAM_s1 | cpu_0_instruction_master_read_data_valid_data_RAM_s1 | ~cpu_0_instruction_master_requests_data_RAM_s1) & (cpu_0_instruction_master_granted_data_RAM_s1 | ~cpu_0_instruction_master_qualified_request_data_RAM_s1) & ((~cpu_0_instruction_master_qualified_request_data_RAM_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_data_RAM_s1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_firmware_ROM_s1 | cpu_0_instruction_master_read_data_valid_firmware_ROM_s1 | ~cpu_0_instruction_master_requests_firmware_ROM_s1) & (cpu_0_instruction_master_granted_firmware_ROM_s1 | ~cpu_0_instruction_master_qualified_request_firmware_ROM_s1) & ((~cpu_0_instruction_master_qualified_request_firmware_ROM_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_firmware_ROM_s1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_payload_buffer_s1 | (cpu_0_instruction_master_read_data_valid_payload_buffer_s1 & cpu_0_instruction_master_dbs_address[1]) | ~cpu_0_instruction_master_requests_payload_buffer_s1);

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_instruction_master_run = r_0 & r_1;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = (cpu_0_instruction_master_granted_payload_buffer_s1 | ~cpu_0_instruction_master_qualified_request_payload_buffer_s1) & ((~cpu_0_instruction_master_qualified_request_payload_buffer_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_payload_buffer_s1 & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 & cpu_0_instruction_master_dbs_address[1]) | ~cpu_0_instruction_master_requests_cfi_flash_0_s1) & (cpu_0_instruction_master_granted_cfi_flash_0_s1 | ~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1) & ((~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_instruction_master_address_to_slave = {cpu_0_instruction_master_address[27],
    2'b0,
    cpu_0_instruction_master_address[24 : 0]};

  //dummy sink, which is an e_mux
  assign dummy_sink = cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_data_RAM_s1 |
    cpu_0_instruction_master_qualified_request_data_RAM_s1 |
    d1_data_RAM_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_firmware_ROM_s1 |
    cpu_0_instruction_master_qualified_request_firmware_ROM_s1 |
    d1_firmware_ROM_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_payload_buffer_s1 |
    cpu_0_instruction_master_qualified_request_payload_buffer_s1 |
    d1_payload_buffer_s1_end_xfer |
    cpu_0_instruction_master_address_to_slave |
    cpu_0_instruction_master_requests_cfi_flash_0_s1 |
    cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 |
    d1_tri_state_bridge_0_avalon_slave_end_xfer |
    cfi_flash_0_s1_wait_counter_eq_0;

  //cpu_0/instruction_master readdata mux, which is an e_mux
  assign cpu_0_instruction_master_readdata = ({32 {~cpu_0_instruction_master_requests_data_RAM_s1}} | data_RAM_s1_readdata_from_sa) &
    ({32 {~cpu_0_instruction_master_requests_firmware_ROM_s1}} | firmware_ROM_s1_readdata_from_sa) &
    ({32 {~cpu_0_instruction_master_requests_payload_buffer_s1}} | {payload_buffer_s1_readdata_from_sa,
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_0_instruction_master_requests_cfi_flash_0_s1}} | {incoming_tri_state_bridge_0_data,
    dbs_16_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;

  //input to dbs-16 stored 0, which is an e_mux
  assign p1_dbs_16_reg_segment_0 = (cpu_0_instruction_master_requests_payload_buffer_s1)? payload_buffer_s1_readdata_from_sa :
    incoming_tri_state_bridge_0_data;

  //dbs register for dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_16_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_0_instruction_master_dbs_address[1]) == 0))
          dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_0_instruction_master_dbs_increment = (cpu_0_instruction_master_requests_payload_buffer_s1)? 2 :
    (cpu_0_instruction_master_requests_cfi_flash_0_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_0_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_0_instruction_master_dbs_address + cpu_0_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_0_instruction_master_dbs_address <= next_dbs_address;
    end


  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = cpu_0_instruction_master_read_data_valid_payload_buffer_s1 |
    cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_0_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_address_last_time <= 0;
      else if (1)
          cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
    end


  //cpu_0/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
    end


  //cpu_0_instruction_master_address matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_0_instruction_master_address or cpu_0_instruction_master_address_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_0_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_instruction_master_read_last_time <= 0;
      else if (1)
          cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
    end


  //cpu_0_instruction_master_read matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_0_instruction_master_read or cpu_0_instruction_master_read_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

  // synthesis attribute cpu_0_instruction_master_arbitrator auto_dissolve FALSE

endmodule


module data_RAM_s1_arbitrator (
                                // inputs:
                                 clk,
                                 cpu_0_data_master_address_to_slave,
                                 cpu_0_data_master_byteenable,
                                 cpu_0_data_master_read,
                                 cpu_0_data_master_waitrequest,