cpu_0_data_master_write,
                                 cpu_0_data_master_writedata,
                                 cpu_0_instruction_master_address_to_slave,
                                 cpu_0_instruction_master_read,
                                 data_RAM_s1_readdata,
                                 reset_n,

                                // outputs:
                                 cpu_0_data_master_granted_data_RAM_s1,
                                 cpu_0_data_master_qualified_request_data_RAM_s1,
                                 cpu_0_data_master_read_data_valid_data_RAM_s1,
                                 cpu_0_data_master_requests_data_RAM_s1,
                                 cpu_0_instruction_master_granted_data_RAM_s1,
                                 cpu_0_instruction_master_qualified_request_data_RAM_s1,
                                 cpu_0_instruction_master_read_data_valid_data_RAM_s1,
                                 cpu_0_instruction_master_requests_data_RAM_s1,
                                 d1_data_RAM_s1_end_xfer,
                                 data_RAM_s1_address,
                                 data_RAM_s1_byteenable,
                                 data_RAM_s1_chipselect,
                                 data_RAM_s1_clken,
                                 data_RAM_s1_readdata_from_sa,
                                 data_RAM_s1_write,
                                 data_RAM_s1_writedata,
                                 registered_cpu_0_data_master_read_data_valid_data_RAM_s1
                              );

  output           cpu_0_data_master_granted_data_RAM_s1;
  output           cpu_0_data_master_qualified_request_data_RAM_s1;
  output           cpu_0_data_master_read_data_valid_data_RAM_s1;
  output           cpu_0_data_master_requests_data_RAM_s1;
  output           cpu_0_instruction_master_granted_data_RAM_s1;
  output           cpu_0_instruction_master_qualified_request_data_RAM_s1;
  output           cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  output           cpu_0_instruction_master_requests_data_RAM_s1;
  output           d1_data_RAM_s1_end_xfer;
  output  [  7: 0] data_RAM_s1_address;
  output  [  3: 0] data_RAM_s1_byteenable;
  output           data_RAM_s1_chipselect;
  output           data_RAM_s1_clken;
  output  [ 31: 0] data_RAM_s1_readdata_from_sa;
  output           data_RAM_s1_write;
  output  [ 31: 0] data_RAM_s1_writedata;
  output           registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            clk;
  input   [ 27: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 27: 0] cpu_0_instruction_master_address_to_slave;
  input            cpu_0_instruction_master_read;
  input   [ 31: 0] data_RAM_s1_readdata;
  input            reset_n;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_data_RAM_s1;
  wire             cpu_0_data_master_qualified_request_data_RAM_s1;
  wire             cpu_0_data_master_read_data_valid_data_RAM_s1;
  reg              cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
  wire             cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in;
  wire             cpu_0_data_master_requests_data_RAM_s1;
  wire             cpu_0_data_master_saved_grant_data_RAM_s1;
  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_data_RAM_s1;
  wire             cpu_0_instruction_master_qualified_request_data_RAM_s1;
  wire             cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  reg              cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in;
  wire             cpu_0_instruction_master_requests_data_RAM_s1;
  wire             cpu_0_instruction_master_saved_grant_data_RAM_s1;
  reg              d1_data_RAM_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire    [  7: 0] data_RAM_s1_address;
  wire             data_RAM_s1_allgrants;
  wire             data_RAM_s1_allow_new_arb_cycle;
  wire             data_RAM_s1_any_continuerequest;
  reg     [  1: 0] data_RAM_s1_arb_addend;
  wire             data_RAM_s1_arb_counter_enable;
  reg     [  1: 0] data_RAM_s1_arb_share_counter;
  wire    [  1: 0] data_RAM_s1_arb_share_counter_next_value;
  wire    [  1: 0] data_RAM_s1_arb_share_set_values;
  wire    [  1: 0] data_RAM_s1_arb_winner;
  wire             data_RAM_s1_arbitration_holdoff_internal;
  wire             data_RAM_s1_beginbursttransfer_internal;
  wire             data_RAM_s1_begins_xfer;
  wire    [  3: 0] data_RAM_s1_byteenable;
  wire             data_RAM_s1_chipselect;
  wire    [  3: 0] data_RAM_s1_chosen_master_double_vector;
  wire    [  1: 0] data_RAM_s1_chosen_master_rot_left;
  wire             data_RAM_s1_clken;
  wire             data_RAM_s1_end_xfer;
  wire             data_RAM_s1_firsttransfer;
  wire    [  1: 0] data_RAM_s1_grant_vector;
  wire             data_RAM_s1_in_a_read_cycle;
  wire             data_RAM_s1_in_a_write_cycle;
  wire    [  1: 0] data_RAM_s1_master_qreq_vector;
  wire    [ 31: 0] data_RAM_s1_readdata_from_sa;
  reg     [  1: 0] data_RAM_s1_saved_chosen_master_vector;
  reg              data_RAM_s1_slavearbiterlockenable;
  wire             data_RAM_s1_waits_for_read;
  wire             data_RAM_s1_waits_for_write;
  wire             data_RAM_s1_write;
  wire    [ 31: 0] data_RAM_s1_writedata;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_0_data_master_granted_slave_data_RAM_s1;
  reg              last_cycle_cpu_0_instruction_master_granted_slave_data_RAM_s1;
  wire             p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
  wire             p1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
  wire             registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  wire             wait_for_data_RAM_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~data_RAM_s1_end_xfer;
    end


  assign data_RAM_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_data_RAM_s1 | cpu_0_instruction_master_qualified_request_data_RAM_s1));
  assign cpu_0_data_master_requests_data_RAM_s1 = ({cpu_0_data_master_address_to_slave[27 : 10] , 10'b0} == 28'h10000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign data_RAM_s1_readdata_from_sa = data_RAM_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign data_RAM_s1_readdata_from_sa = data_RAM_s1_readdata;

  //registered rdv signal_name registered_cpu_0_data_master_read_data_valid_data_RAM_s1 assignment, which is an e_assign
  assign registered_cpu_0_data_master_read_data_valid_data_RAM_s1 = cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in;

  //data_RAM_s1_arb_share_counter set values, which is an e_mux
  assign data_RAM_s1_arb_share_set_values = 1;

  //data_RAM_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign data_RAM_s1_arb_share_counter_next_value = data_RAM_s1_firsttransfer ? (data_RAM_s1_arb_share_set_values - 1) : |data_RAM_s1_arb_share_counter ? (data_RAM_s1_arb_share_counter - 1) : 0;

  //data_RAM_s1_allgrants all slave grants, which is an e_mux
  assign data_RAM_s1_allgrants = |data_RAM_s1_grant_vector |
    |data_RAM_s1_grant_vector |
    |data_RAM_s1_grant_vector |
    |data_RAM_s1_grant_vector;

  //data_RAM_s1_end_xfer assignment, which is an e_assign
  assign data_RAM_s1_end_xfer = ~(data_RAM_s1_waits_for_read | data_RAM_s1_waits_for_write);

  //data_RAM_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign data_RAM_s1_arb_counter_enable = data_RAM_s1_end_xfer & data_RAM_s1_allgrants;

  //data_RAM_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_RAM_s1_arb_share_counter <= 0;
      else if (data_RAM_s1_arb_counter_enable)
          data_RAM_s1_arb_share_counter <= data_RAM_s1_arb_share_counter_next_value;
    end


  //data_RAM_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_RAM_s1_slavearbiterlockenable <= 0;
      else if (|data_RAM_s1_master_qreq_vector & data_RAM_s1_end_xfer)
          data_RAM_s1_slavearbiterlockenable <= |data_RAM_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master data_RAM/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = data_RAM_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //cpu_0/instruction_master data_RAM/s1 arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = data_RAM_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //cpu_0/instruction_master granted data_RAM/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_0_instruction_master_granted_slave_data_RAM_s1 <= 0;
      else if (1)
          last_cycle_cpu_0_instruction_master_granted_slave_data_RAM_s1 <= cpu_0_instruction_master_saved_grant_data_RAM_s1 ? 1 : (data_RAM_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_data_RAM_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_data_RAM_s1;
    end


  //cpu_0_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_data_RAM_s1 & cpu_0_instruction_master_requests_data_RAM_s1;

  //data_RAM_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  assign data_RAM_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
    cpu_0_data_master_continuerequest;

  assign cpu_0_data_master_qualified_request_data_RAM_s1 = cpu_0_data_master_requests_data_RAM_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
  //cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in = cpu_0_data_master_granted_data_RAM_s1 & cpu_0_data_master_read & ~data_RAM_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register);

  //shift register p1 cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register = {cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register, cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in};

  //cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register <= 0;
      else if (1)
          cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
    end


  //local readdatavalid cpu_0_data_master_read_data_valid_data_RAM_s1, which is an e_mux
  assign cpu_0_data_master_read_data_valid_data_RAM_s1 = cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;

  //data_RAM_s1_writedata mux, which is an e_mux
  assign data_RAM_s1_writedata = cpu_0_data_master_wr