?? freedev_cycloneii_50.ptf
字號:
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "4.0";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x00040000";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>2D2E8035</b> (unique ID tag) <br> <b>44DC4F03</b> (timestamp: Fri Aug 11, 2006 @5:33 PM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
value0 = "1686625497u";
value1 = "1079118575u";
id = "758022197u";
timestamp = "1155288835u";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x00040000 --id=758022197 --timestamp=1155288835";
Is_Phony = "1";
Target_File = "dummy_verifysysid_file";
}
}
}
}
}
MODULE asmi
{
class = "altera_avalon_asmi";
class_version = "2.1";
SLAVE asmi_control_port
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Nonvolatile_Storage = "1";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00060000";
Is_Base_Locked = "1";
}
PORT_WIRING
{
PORT asmi_select
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT data_from_cpu
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
PORT data_to_cpu
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
Is_Enabled = "1";
}
PORT endofpacket
{
direction = "output";
type = "endofpacket";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT mem_addr
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_asmi";
flash_reference_designator = "U59";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXII";
Fixed_Module_Name = "asmi";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
databits = "8";
targetclock = "20";
clockunits = "MHz";
clockmult = "1000000";
numslaves = "1";
ismaster = "1";
clockpolarity = "0";
clockphase = "0";
lsbfirst = "0";
extradelay = "1";
targetssdelay = "100";
delayunits = "us";
delaymult = "1e-006";
prefix = "asmi_";
CONSTANTS
{
CONSTANT na_asmi_64K
{
value = "0";
comment = "ASMI part is 64k bits";
}
CONSTANT na_asmi_1M
{
value = "0";
comment = "ASMI part is 1M bits";
}
CONSTANT na_asmi_4M
{
value = "1";
comment = "ASMI part is 4M bits";
}
}
clockunit = "kHz";
delayunit = "us";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/asmi.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE Board_System
{
class = "altera_user_board_setup";
class_version = "1.0";
SLAVE bogus_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Component_Name = "freedev_cycloneII_50";
JTAG_device_index = "1";
name1 = "";
slave1 = "";
offset1 = "";
length1 = "";
name2 = "";
slave2 = "";
offset2 = "";
length2 = "";
name3 = "";
slave3 = "";
offset3 = "";
length3 = "";
name4 = "";
slave4 = "";
offset4 = "";
length4 = "";
name5 = "";
slave5 = "";
offset5 = "";
length5 = "";
name6 = "";
slave6 = "";
offset6 = "";
length6 = "";
name7 = "";
slave7 = "";
offset7 = "";
length7 = "";
name8 = "";
slave8 = "";
offset8 = "";
length8 = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "Board_System";
Is_Visible = "0";
View
{
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "clk";
}
}
MODULE tri_state_bridge_0
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
}
MODULE cfi_flash_0
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
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