-- Created on Wed Aug 20 21:28:33 2003
-- turbo jtag for Trimedia TM1300 DSP

TITLE "JTAG_CONTROL";

	INCLUDE "lpm_counter.inc";
	INCLUDE "lpm_shiftreg.inc";
	INCLUDE "lpm_mux.inc";

SUBDESIGN jt
(
	WR: 		INPUT;
	RD: 		INPUT;
	CS: 		INPUT;
	CLK: 		INPUT;		--40MHz
	A[4..0]: 	INPUT;
	ISA_CLK: 	INPUT;		--8MHz
	RESET: 		INPUT;

	SBHE: 		OUTPUT;
	IO_CH_RDY:	OUTPUT;
	IO_CS16: 	OUTPUT;
	D[15..0]: 	BIDIR;

	probe[3..0]:		OUTPUT;		--test

	mTDI: 		OUTPUT;
	mTDO: 		INPUT;
	mTMS:		OUTPUT;
	mTCK:		OUTPUT;
)

VARIABLE
shift_L0:	lpm_shiftreg WITH (LPM_WIDTH = 5, LPM_DIRECTION = "RIGHT");
shift_L1:	lpm_shiftreg WITH (LPM_WIDTH = 3, LPM_DIRECTION = "RIGHT");
shift_L2:	lpm_shiftreg WITH (LPM_WIDTH = 8, LPM_DIRECTION = "RIGHT");
shift_H:	lpm_shiftreg WITH (LPM_WIDTH = 16, LPM_DIRECTION = "RIGHT");
shift_H16:	DFFE;
rdmux:		lpm_mux WITH(LPM_WIDTH = 16, LPM_SIZE = 3, LPM_WIDTHS = 2);
cnt:		lpm_counter WITH (LPM_WIDTH = 6, LPM_DIRECTION = "DOWN");
--Dtck:			DFF;
control1[8..0]:	DFFE;		--8:BYPASS_EXBIT, 7:EXBIT, 6:SCAN_IR, 5..0:LENGTH. addr:4
control2[1..0]:	DFFE;		--6:JTAG_OUTPUT_ENABLE, 0:CTRLRST. addr:6

Dout[15..0]:	TRI;		--for ISA interface
BUSY:			NODE;
shifting_data:	NODE;
CS_data_L:		NODE;		-- 0
CS_data_H:		NODE;		-- 2
CS_control1:	NODE;		-- 4
CS_control2:	NODE;		-- 6
CS_status:		NODE;		-- 8
--CLK2:			NODE;

--scan_ir: 011(n-1)0011
--scan_dr: 011(n-1)001

mm	: MACHINE WITH STATES (
		midle,			--wait input

		mpre0,
		mpre1,
		mpre2,
		mpre3,

		mshift_data,	--shift out data

		mpost0,			--shift out 011, return IDLE state
		mpost1,
		mpost2,

		mreset1,
		mreset2,
		mreset3,
		mreset4
		);

BEGIN
	DEFAULTS
		cnt.sload = GND;
		cnt.cnt_en = GND;

		shifting_data = GND;

		IO_CH_RDY = VCC;

		mTDI = GND;
		mTCK = GND;
		mTMS = GND;
		BUSY = GND;

		control1[].clrn = VCC;
		control2[].clrn = VCC;		

		probe[] = GND;
	END DEFAULTS;

	cnt.clock = CLK;

--	Dtck.clk = CLK;
--	Dtck = !Dtck;
--	CLK2 = !Dtck;

	IO_CS16 = CS # (RD & WR);
	SBHE = CS # (RD & WR);

--ISA common
	CS_data_L = ((A[] == 0) & !CS);
	CS_data_H = ((A[] == 2) & !CS);
	CS_control1 = ((A[] == 4) & !CS);
	CS_control2 = ((A[] == 6) & !CS);
	CS_status = ((A[] == 8) & !CS);

	rdmux.data[0][4..0] = shift_L0.q[4..0];
	rdmux.data[0][7..5] = shift_L1.q[2..0];
	rdmux.data[0][15..8] = shift_L2.q[7..0];
	rdmux.data[1][15..0] = shift_H.q[15..0];
	rdmux.data[2][0] = BUSY;						--status
	rdmux.data[2][6..1] = 0;
	rdmux.data[2][7] = shift_H16.q;

	FOR i IN 0 TO 15 GENERATE
		Dout[i].in = rdmux.result[i];
		Dout[i].oe = !RD & !CS;
		D[i] = Dout[i].out;
	END GENERATE;
--ISA write	
	control1[].clk = WR;
	control1[].ena = CS_control1;
	control1[8..0] = D[8..0];

	control2[].clk = WR;
	control2[].ena = CS_control2;
	control2[1] = D[6];
	control2[0] = D[0];

	shift_L0.data[4..0] = D[4..0];
	shift_L0.load = CS_data_L & !WR;
	shift_L0.clock = GLOBAL(CLK);
	shift_L0.enable = (CS_data_L & !WR) # shifting_data;

	shift_L1.data[2..0] = D[7..5];
	shift_L1.load = CS_data_L & !WR;
	shift_L1.clock = GLOBAL(CLK);
	shift_L1.enable = (CS_data_L & !WR) # shifting_data;

	shift_L2.shiftin = shift_H.shiftout;
	shift_L2.data[7..0] = D[15..8];
	shift_L2.load = CS_data_L & !WR;
	shift_L2.clock = GLOBAL(CLK);
	shift_L2.enable = (CS_data_L & !WR) # shifting_data;

	shift_H.data[15..0] = D[15..0];
	shift_H.load = CS_data_H & !WR;
	shift_H.clock = CLK;
	shift_H.enable = (CS_data_H & !WR) # shifting_data;

	shift_H16.clk = CLK;

--ISA read
	IF 	CS_data_L THEN
		rdmux.sel[] = 0;
	END IF;

	IF 	CS_data_H THEN
		rdmux.sel[] = 1;
	END IF;

	IF 	CS_status THEN
		rdmux.sel[] = 2;
	END IF;

--shift reg
	CASE control1[5..0] IS
		WHEN 5 =>
			shift_L0.shiftin = mTDO;
		WHEN 8 =>
			shift_L0.shiftin = shift_L1.shiftout;
			shift_L1.shiftin = mTDO;
		WHEN 32 =>
			shift_L0.shiftin = shift_L1.shiftout;
			shift_L1.shiftin = shift_L2.shiftout;
			shift_L2.shiftin = shift_H.shiftout;
			shift_H.shiftin = mTDO;
		WHEN 33 =>
			shift_L0.shiftin = shift_L1.shiftout;
			shift_L1.shiftin = shift_L2.shiftout;
			shift_L2.shiftin = shift_H.shiftout;
			shift_H.shiftin = shift_H16.q;
			shift_H16.d = mTDO;
	END CASE;
-----------------------------------------------
	mm.clk = CLK;
	mm.reset = RESET;

	CASE mm IS
		WHEN midle =>
			probe[] = 0;
			IF control2[1..0] == 1 THEN			--reset
				mm = mreset1;
			END IF;

			IF control1[5..0] != 0 THEN			--length != 0, scan data
				IF control1[6] THEN
					mm = mpre0;					--scan ir
				ELSE
					mm = mpre1;					--scan dr
				END IF;
			END IF;

		WHEN mpre0 =>
			probe[] = 1;
			mTMS = VCC;
			mTCK = !CLK;
			BUSY = VCC;
			mm = mpre1;

		WHEN mpre1 =>
			probe[] = 2;
			mTMS = VCC;
			mTCK = !CLK;
			BUSY = VCC;
			mm = mpre2;

		WHEN mpre2 =>
			probe[] = 3;
			mTMS = GND;
			mTCK = !CLK;
			BUSY = VCC;
			mm = mpre3;

		WHEN mpre3 =>
			probe[] = 4;
			mTMS = GND;
			mTCK = !CLK;

			shifting_data = VCC;
			cnt.data[5..0] = control1[5..0];
			shift_H16.d = control1[7];			--ext_bit
			cnt.sload = VCC;
			BUSY = VCC;
			mm = mshift_data;

		WHEN mshift_data =>
			probe[] = 5;
			mTDI = shift_L0.shiftout;
			mTCK = !CLK;
			shifting_data = VCC;
			BUSY = VCC;
			cnt.cnt_en = VCC;

			IF cnt.q[] == 2 THEN
				mm = mpost0;
			END IF;

		WHEN mpost0 =>
			probe[] = 6;
			mTDI = shift_L0.shiftout;
			mTMS = VCC;
			mTCK = !CLK;
			shifting_data = VCC;
			BUSY = VCC;
			mm = mpost1;

		WHEN mpost1 =>
			probe[] = 7;		
			mTMS = VCC;
			mTCK = !CLK;
			BUSY = VCC;
			mm = mpost2;

		WHEN mpost2 =>
			probe[] = 8;
			mTMS = GND;
			mTCK = !CLK;
			BUSY = VCC;
			control1[].clrn = GND;
			mm = midle;

		WHEN mreset1 =>
			probe[] = 9;		
			mTDI = VCC;
			mTCK = !CLK;
			mTCK = VCC;
			mTMS = VCC;

			IF control2[1..0] == 3 THEN
				mm = mreset2;
			END IF;

		WHEN mreset2 =>
			probe[] = 10;
			mTDI = VCC;
			mTCK = !CLK;
			mTMS = VCC;
			
			IF control2[1..0] == 2 THEN
				mm = mreset3;
			END IF;

		WHEN mreset3 =>
			probe[] = 11;
			mTDI = VCC;
			mTCK = GND;
			mTMS = GND;
			mm = mreset4;

		WHEN mreset4 =>
			probe[] = 12;
			mTDI = VCC;
			mTCK = VCC;
			mTMS = GND;
			control2[].clrn = GND;
			mm = midle;

		WHEN OTHERS =>
			probe[] = 13;
			control1[].clrn = GND;
			control2[].clrn = GND;
			mm = midle;

	END CASE;
END;