module diviodd(clk_in, rst, clk_out);
input clk_in, rst;
output clk_out;
reg[2:0] counter, countern;
reg temp, temn;
parameter N = 3;

always@(posedge clk_in)//產(chǎn)生占空比2：1的3分頻temp
	if(!rst) begin
		counter <= 0;
		temp <= 0;
		end
	else begin
		if(counter < N-1) begin
			counter <= counter + 1;
			temp <= 1;
			end
		else begin
			counter <= 0;
			temp <= 0;
			end
	end

always@(negedge clk_in)//產(chǎn)生占空比2:1的3分頻temn
	if(!rst)
		temn <= 0;
	else
		temn <= temp;
assign clk_out = temp & temn;//產(chǎn)生占空比1:1的3分頻

endmodule