`timescale 1 ps / 1ps

module ADI_Clocking_RevD(
	rstin,
	phase_en,
	phase_incdec,
	ps_done,
	ps_overflow,
	res_sel_0,
	res_sel_1,
	rxclkin,
	data_in,
	frame_in,
	data_out_a,
	data_out_b,
	data_out_c,
	data_out_d,
	fco_clk,
	rxclk
	);	

input rstin, rxclkin, frame_in;
input phase_en, phase_incdec;
input res_sel_0, res_sel_1;
input [3:0] data_in;

output [13:0] data_out_a, data_out_b, data_out_c, data_out_d;
output fco_clk, rxclk, ps_done, ps_overflow;
			
wire rxclk_p, rxclk_n;
wire fco_latch_temp14, fco_latch_temp12;
wire fco_latch_temp10, fco_latch_temp8;
wire fco_en_p_temp14, fco_en_n_temp14;					
wire fco_en_p_temp12, fco_en_n_temp12;					
wire fco_en_p_temp10, fco_en_n_temp10;					
wire fco_en_p_temp8, fco_en_n_temp8;					
wire rxclkdcm_p, rxclkdcm_n, rstint;
wire ps_overflow, phase_en_buf, phase_incdec_buf;
wire [7:0] ps_or;
	
reg fco_clk, rst_edge, term_count, count_en;
reg term_cnt, cnt_en, ps_clk;
reg [19:0] count;
reg [18:0] cnt;		

// Buffer for input controls
IBUF_LVCMOS33 rstinbuf(.O(rstint), .I(rstin));
IBUF_LVCMOS33 psenbuf(.O(phase_en_buf), .I(phase_en));
IBUF_LVCMOS33 psincdecbuf(.O(phase_incdec_buf), .I(phase_incdec));

// Debounce reset button
always @(posedge rstint or posedge term_count)
	if(term_count)
		count_en <= 0;
	else
		count_en <= 1;
	
always @(posedge frame_in)
	if(term_count)
		count <= 0;
	else if(count_en)
		count <= count + 1;

always @(posedge frame_in)
	if(count == 20'hfffff)
		term_count <= 1;
	else
		term_count <= 0;

always @(posedge frame_in)
	if(count > 0)
		rst_edge <= 1;
	else
		rst_edge <= 0;

// Divide psclk 
always @(posedge frame_in or posedge term_cnt)
	if(term_cnt)
		cnt_en <= 0;
	else
		cnt_en <= 1;
	
always @(posedge frame_in)
	if(term_cnt)
		cnt <= 0;
	else if(cnt_en)
		cnt <= cnt + 1;

always @(posedge frame_in)
	if(cnt == 19'h7ffff)
		term_cnt <= 1;
	else
		term_cnt <= 0;

always @(posedge frame_in)
	if(cnt > 19'h3ffff)
		ps_clk <= 1;
	else
		ps_clk <= 0;

DCM dcm_rxclk(
	.CLKIN(rxclkin),
	.CLKFB(rxclk_p),
	.RST(rst_edge),
	.PSCLK(ps_clk),
	.PSEN(phase_en_buf),
	.PSINCDEC(phase_incdec_buf),
	.PSDONE(ps_done),
	.STATUS(ps_or),
	.CLK0(rxclkdcm_p),
	.CLK180(rxclkdcm_n)); 

assign ps_overflow = ps_or[0];

// set up positive and negative edge clocks
BUFGMUX rxclk_bufg_p(.O(rxclk_p), .I0(rxclkdcm_p), .I1(1'b0), .S(1'b0)); 
BUFGMUX rxclk_bufg_n(.O(rxclk_n), .I0(rxclkdcm_n), .I1(1'b0), .S(1'b0));

// set up delayed clocks for frame alignment
FD frame_ff1p(.C(rxclk_p), .D(frame_in), .Q(frame_1p));	
FD frame_ff2p(.C(rxclk_p), .D(frame_1p), .Q(frame_2p));
FD frame_ff3p(.C(rxclk_p), .D(frame_2p), .Q(frame_3p));
FD frame_ff4p(.C(rxclk_p), .D(frame_3p), .Q(frame_4p));
FD frame_ff5p(.C(rxclk_p), .D(frame_4p), .Q(frame_5p));

FD frame_ff1n(.C(rxclk_n), .D(frame_in), .Q(frame_1n));	
FD frame_ff2n(.C(rxclk_n), .D(frame_1n), .Q(frame_2n));
FD frame_ff3n(.C(rxclk_n), .D(frame_2n), .Q(frame_3n));
FD frame_ff4n(.C(rxclk_n), .D(frame_3n), .Q(frame_4n));

// select data format and resolution for final data clock
// Using temporary placeholder for 14-bit ADC
always @(posedge rxclk_p)
	case({res_sel_1, res_sel_0})
		2'b11 : fco_clk <= frame_3p; // 14-bits
		2'b10 : fco_clk <= frame_3p; // 12-bits
		2'b01 : fco_clk <= frame_4p; // 10-bits
		2'b00 : fco_clk <= frame_5p; //  8-bits
	endcase

reg fco_en_p, fco_en_n;

assign fco_en_p_temp14 = frame_1p & !frame_2p; 
assign fco_en_p_temp12 = frame_1p & !frame_2p; 
assign fco_en_p_temp10 = frame_2p & !frame_3p; 
assign fco_en_p_temp8 = frame_3p & !frame_4p; 

// select data format and resolution for positive edge parallel data clock
always @(posedge rxclk_p)
	case({res_sel_1, res_sel_0})
		2'b11 : fco_en_p <= fco_en_p_temp14;
		2'b10 : fco_en_p <= fco_en_p_temp12;
		2'b01 : fco_en_p <= fco_en_p_temp10;
		2'b00 : fco_en_p <= fco_en_p_temp8;
	endcase

assign fco_en_n_temp14 = frame_1n & !frame_2n; 
assign fco_en_n_temp12 = frame_1n & !frame_2n; 
assign fco_en_n_temp10 = frame_2n & !frame_3n; 
assign fco_en_n_temp8 = frame_3n & !frame_4n; 

// select data format and resolution for negative edge parallel data clock
always @(posedge rxclk_n)
	case({res_sel_1, res_sel_0})
  		2'b11 : fco_en_n <= fco_en_n_temp14;
   		2'b10 : fco_en_n <= fco_en_n_temp12;
   		2'b01 : fco_en_n <= fco_en_n_temp10;
   		2'b00 : fco_en_n <= fco_en_n_temp8;
	endcase

reg fco_latch;

assign fco_latch_temp14 = !frame_1p & frame_2p;
assign fco_latch_temp12 = !frame_1p & frame_2p;
assign fco_latch_temp10 = !frame_2p & frame_3p;
assign fco_latch_temp8 = !frame_3p & frame_4p;

// select data format and resolution for initial full parallel data clock
always @(posedge rxclk_p)
	case({res_sel_1, res_sel_0})
		2'b11 : fco_latch <= fco_latch_temp14;
		2'b10 : fco_latch <= fco_latch_temp12;
		2'b01 : fco_latch <= fco_latch_temp10;
		2'b00 : fco_latch <= fco_latch_temp8;
	endcase

assign rxclk = rxclk_p;

// shift and deserialize data
ADI_Shift_RevD rx0 (
	.data_in(data_in),
	.rxclk_p(rxclk_p),
	.rxclk_n(rxclk_n),
	.fco_en_p(fco_en_p),
	.fco_en_n(fco_en_n),
	.par_data_a(data_out_a),
	.par_data_b(data_out_b),
	.par_data_c(data_out_c),
	.par_data_d(data_out_d),
	.fco_latch(fco_latch));

endmodule