# Assign pins and properties
INST "fd_out_ab13" IOB = TRUE ;
INST "fd_out_ab12" IOB = TRUE ;
INST "fd_out_ab11" IOB = TRUE ;
INST "fd_out_ab10" IOB = TRUE ;
INST "fd_out_ab09" IOB = TRUE ;
INST "fd_out_ab08" IOB = TRUE ;
INST "fd_out_ab07" IOB = TRUE ;
INST "fd_out_ab06" IOB = TRUE ;
INST "fd_out_ab05" IOB = TRUE ;
INST "fd_out_ab04" IOB = TRUE ;
INST "fd_out_ab03" IOB = TRUE ;
INST "fd_out_ab02" IOB = TRUE ;
INST "fd_out_ab01" IOB = TRUE ;
INST "fd_out_ab00" IOB = TRUE ;

INST "fd_out_cd13" IOB = TRUE ;
INST "fd_out_cd12" IOB = TRUE ;
INST "fd_out_cd11" IOB = TRUE ;
INST "fd_out_cd10" IOB = TRUE ;
INST "fd_out_cd09" IOB = TRUE ;
INST "fd_out_cd08" IOB = TRUE ;
INST "fd_out_cd07" IOB = TRUE ;
INST "fd_out_cd06" IOB = TRUE ;
INST "fd_out_cd05" IOB = TRUE ;
INST "fd_out_cd04" IOB = TRUE ;
INST "fd_out_cd03" IOB = TRUE ;
INST "fd_out_cd02" IOB = TRUE ;
INST "fd_out_cd01" IOB = TRUE ;
INST "fd_out_cd00" IOB = TRUE ;

INST "ADI_Clocking_inst/dcm_rxclk" DUTY_CYCLE_CORRECTION = "TRUE" |
		CLKOUT_PHASE_SHIFT = "VARIABLE" | PHASE_SHIFT = "50" |
		DLL_FREQUENCY_MODE = "HIGH" | CLK_FEEDBACK = "1X" |
		DESKEW_ADJUST = SOURCE_SYNCHRONOUS | LOC = "DCM_X1Y1" ;

NET "res_sel_0" LOC = "T5" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "res_sel_1" LOC = "T6" | IOSTANDARD = LVCMOS33 | PULLUP ;

NET "phase_en" LOC = "A10" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "phase_incdec" LOC = "A7" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "ps_done" LOC = "B6" | IOSTANDARD = LVCMOS33 ;
NET "ps_overflow" LOC = "A6" | IOSTANDARD = LVCMOS33 ;

NET "dco_p"  LOC = "A8" | IOSTANDARD = LVDS_33 | TNM_NET = "dco_p" ;	
NET "fco_p"  LOC = "C8" | IOSTANDARD = LVDS_33 ;

NET "din_a_p"  LOC = "E1" | IOSTANDARD = LVDS_33 ;
NET "din_b_p"  LOC = "F1" | IOSTANDARD = LVDS_33 ;
NET "din_c_p"  LOC = "G1" | IOSTANDARD = LVDS_33 ;
NET "din_d_p"  LOC = "H1" | IOSTANDARD = LVDS_33 ;

NET "rst"  LOC = "T12" | IOSTANDARD = LVCMOS33  | PULLUP ;
NET "sel_ab"  LOC = "T10" | IOSTANDARD = LVCMOS33  | PULLUP ;
NET "sel_cd"  LOC = "T11" | IOSTANDARD = LVCMOS33  | PULLUP ;

NET "clk_ab"  LOC = "C16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<0>"  LOC = "H16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<1>"  LOC = "H15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<2>"  LOC = "H14" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<3>"  LOC = "H13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<4>"  LOC = "G15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<5>"  LOC = "G14" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<6>"  LOC = "G13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<7>"  LOC = "F16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<8>"  LOC = "F15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<9>"  LOC = "F14" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<10>"  LOC = "F13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<11>"  LOC = "E16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<12>"  LOC = "E15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_ab<13>"  LOC = "E13" | IOSTANDARD = LVCMOS33 ;

NET "clk_cd"  LOC = "J13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<0>"  LOC = "P16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<1>"  LOC = "N16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<2>"  LOC = "M16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<3>"  LOC = "M15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<4>"  LOC = "M13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<5>"  LOC = "L16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<6>"  LOC = "L15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<7>"  LOC = "L14" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<8>"  LOC = "L13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<9>"  LOC = "K15" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<10>"  LOC = "K14" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<11>"  LOC = "K13" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<12>"  LOC = "J16" | IOSTANDARD = LVCMOS33 ;
NET "out_data_cd<13>"  LOC = "J15" | IOSTANDARD = LVCMOS33 ;

# Assign timing constraints
TIMESPEC "TS_dco_p" = PERIOD "dco_p" 420 MHz HIGH 50% ;	
NET "fco_p" TNM_NET = "fco_p";
TIMESPEC "TS_fco_p" = PERIOD "fco_p" 65 MHz HIGH 50% ;	
OFFSET = IN 0 ns VALID 1.19 ns BEFORE "dco_p" ;		 
NET "sel_ab" OFFSET = IN 10 ns BEFORE "dco_p"  ;	 
NET "sel_cd" OFFSET = IN 10 ns BEFORE "dco_p"  ;	 
OFFSET = OUT 10 ns AFTER "dco_p" ;						 

NET "res_sel_0" OFFSET = IN 10 ns BEFORE "dco_p" ;
NET "res_sel_1" OFFSET = IN 10 ns BEFORE "dco_p" ;
  
NET "ADI_Clocking_inst/rxclk_n" TNM_NET = "rxclk_n_grp" ;
INST "din_*" TNM = "negedge_input_pads" ;
INST "fco_p" TNM = "negedge_input_pads" ;
INST "fco_n" TNM = "negedge_input_pads" ;

TIMEGRP "negedge_input_pads" OFFSET = IN -1.19 ns VALID 1.19 ns BEFORE "dco_p" TIMEGRP "rxclk_n_grp" ; 

INST "ADI_Clocking_inst/rx0/dout???_x" TNM = "fco_latch_delay" ;
INST "fd_out_*" TNM = "data_out_flops" ;
TIMEGRP "cust_access_grp" = FFS("data_out_mux_*") ;

TIMESPEC "TS_ffs_to_fcp_del" = FROM "adj_fco_ff_grp" TO "fco_latch_delay" "TS_dco_p" / 1.0 ;	
TIMESPEC "TS_ffs_to_cust_data_del" = FROM "adj_fco_ff_grp" TO "cust_access_grp" "TS_dco_p" / 1.5 ;	
TIMESPEC "TS_ffs_to_fc_del" = FROM "adj_fco_del_grp" TO "data_out_flops" "TS_dco_p" / 2.0 ;	

INST "ADI_Clocking_inst/fco_clk*" TNM = "fco_ff_grp" ;
INST "ADI_Clocking_inst/fco_latch*" TNM = "fco_ff_grp" ;
TIMEGRP "adj_fco_ff_grp" = FFS EXCEPT "fco_ff_grp" ;
INST "fco_del" TNM = "fco_del_grp";
TIMEGRP "adj_fco_del_grp" = FFS EXCEPT "fco_del_grp" ;

# Assign location constraints
#INST "ADI_Clocking_inst/count*" AREA_GROUP = "counter_area" ;
#INST "ADI_Clocking_inst/term*" AREA_GROUP = "counter_area" ;
#INST "ADI_Clocking_inst/rst*" AREA_GROUP = "counter_area" ;
#AREA_GROUP "counter_area" RANGE = SLICE_X14Y42:SLICE_X17Y47 ;

#RLOC_ORIGIN Col = 31, Row = 20 ;
INST "muxf5_cd08" RLOC_ORIGIN = "X31Y20" ;
INST "muxf5_ab13" RLOC = "X-1Y20" ;
INST "muxf5_ab12" RLOC = "X-1Y19" ;
INST "muxf5_ab11" RLOC = "X-1Y18" ;
INST "muxf5_ab10" RLOC = "X-1Y17" ;
INST "muxf5_ab09" RLOC = "X-1Y16" ;
INST "muxf5_ab08" RLOC = "X-1Y15" ;
INST "muxf5_ab07" RLOC = "X-1Y14" ;
INST "muxf5_ab06" RLOC = "X-1Y13" ;
INST "muxf5_ab05" RLOC = "X-1Y12" ;
INST "muxf5_ab04" RLOC = "X-1Y11" ;
INST "muxf5_ab03" RLOC = "X-1Y10" ;
INST "muxf5_ab02" RLOC = "X-1Y9" ;
INST "muxf5_ab01" RLOC = "X-1Y8" ;
INST "muxf5_ab00" RLOC = "X-1Y7" ;

INST "muxf5_cd13" RLOC = "X-1Y5" ;
INST "muxf5_cd12" RLOC = "X-1Y4" ;
INST "muxf5_cd11" RLOC = "X-1Y3" ;
INST "muxf5_cd10" RLOC = "X-1Y2" ;
INST "muxf5_cd09" RLOC = "X-1Y1" ;
INST "muxf5_cd08" RLOC = "X-1Y0" ;
INST "muxf5_cd07" RLOC = "X-1Y-1" ;
INST "muxf5_cd06" RLOC = "X-1Y-2" ;
INST "muxf5_cd05" RLOC = "X-1Y-3" ;
INST "muxf5_cd04" RLOC = "X-1Y-4" ;
INST "muxf5_cd03" RLOC = "X-1Y-5" ;
INST "muxf5_cd02" RLOC = "X-1Y-6" ;
INST "muxf5_cd01" RLOC = "X-1Y-7" ;
INST "muxf5_cd00" RLOC = "X-1Y-8" ;

INST "data_out_mux_d_13" RLOC = "X-2Y4" ;
INST "data_out_mux_d_12" RLOC = "X-3Y4" ;
INST "data_out_mux_d_11" RLOC = "X-2Y2" ;
INST "data_out_mux_d_10" RLOC = "X-3Y2" ;
INST "data_out_mux_d_9" RLOC = "X-2Y0" ;
INST "data_out_mux_d_8" RLOC = "X-3Y0" ;
INST "data_out_mux_d_7" RLOC = "X-2Y-2" ;
INST "data_out_mux_d_6" RLOC = "X-3Y-2" ;
INST "data_out_mux_d_5" RLOC = "X-2Y-4" ;
INST "data_out_mux_d_4" RLOC = "X-3Y-4" ;
INST "data_out_mux_d_3" RLOC = "X-2Y-6" ;
INST "data_out_mux_d_2" RLOC = "X-3Y-6" ;
INST "data_out_mux_d_1" RLOC = "X-2Y-8" ;
INST "data_out_mux_d_0" RLOC = "X-3Y-8" ;

INST "data_out_mux_c_13" RLOC = "X-2Y5" ;
INST "data_out_mux_c_12" RLOC = "X-3Y5" ;
INST "data_out_mux_c_11" RLOC = "X-2Y3" ;
INST "data_out_mux_c_10" RLOC = "X-3Y3" ;
INST "data_out_mux_c_9" RLOC = "X-2Y1" ;
INST "data_out_mux_c_8" RLOC = "X-3Y1" ;
INST "data_out_mux_c_7" RLOC = "X-2Y-1" ;
INST "data_out_mux_c_6" RLOC = "X-3Y-1" ;
INST "data_out_mux_c_5" RLOC = "X-2Y-3" ;
INST "data_out_mux_c_4" RLOC = "X-3Y-3" ;
INST "data_out_mux_c_3" RLOC = "X-2Y-5" ;
INST "data_out_mux_c_2" RLOC = "X-3Y-5" ;
INST "data_out_mux_c_1" RLOC = "X-2Y-7" ;
INST "data_out_mux_c_0" RLOC = "X-3Y-7" ;

INST "data_out_mux_b_13" RLOC = "X-2Y20" ;
INST "data_out_mux_b_12" RLOC = "X-3Y19" ;
INST "data_out_mux_b_11" RLOC = "X-2Y17" ;
INST "data_out_mux_b_10" RLOC = "X-3Y17" ;
INST "data_out_mux_b_9" RLOC = "X-2Y15" ;
INST "data_out_mux_b_8" RLOC = "X-3Y15" ;
INST "data_out_mux_b_7" RLOC = "X-2Y13" ;
INST "data_out_mux_b_6" RLOC = "X-3Y13" ;
INST "data_out_mux_b_5" RLOC = "X-2Y11" ;
INST "data_out_mux_b_4" RLOC = "X-3Y11" ;
INST "data_out_mux_b_3" RLOC = "X-2Y9" ;
INST "data_out_mux_b_2" RLOC = "X-3Y9" ;
INST "data_out_mux_b_1" RLOC = "X-2Y7" ;
INST "data_out_mux_b_0" RLOC = "X-3Y7" ;

INST "data_out_mux_a_13" RLOC = "X-2Y21" ;
INST "data_out_mux_a_12" RLOC = "X-3Y20" ;
INST "data_out_mux_a_11" RLOC = "X-2Y18" ;
INST "data_out_mux_a_10" RLOC = "X-3Y18" ;
INST "data_out_mux_a_9" RLOC = "X-2Y16" ;
INST "data_out_mux_a_8" RLOC = "X-3Y16" ;
INST "data_out_mux_a_7" RLOC = "X-2Y14" ;
INST "data_out_mux_a_6" RLOC = "X-3Y14" ;
INST "data_out_mux_a_5" RLOC = "X-2Y12" ;
INST "data_out_mux_a_4" RLOC = "X-3Y12" ;
INST "data_out_mux_a_3" RLOC = "X-2Y10" ;
INST "data_out_mux_a_2" RLOC = "X-3Y10" ;
INST "data_out_mux_a_1" RLOC = "X-2Y8" ;
INST "data_out_mux_a_0" RLOC = "X-3Y8" ;

INST "ADI_Clocking_inst/rx0/dout13d_x" RLOC = "X-21Y5" ;
INST "ADI_Clocking_inst/rx0/dout12d_x" RLOC = "X-21Y4" ;
INST "ADI_Clocking_inst/rx0/dout11d_x" RLOC = "X-20Y3" ;
INST "ADI_Clocking_inst/rx0/dout10d_x" RLOC = "X-20Y2" ;
INST "ADI_Clocking_inst/rx0/dout09d_x" RLOC = "X-21Y3" ;
INST "ADI_Clocking_inst/rx0/dout08d_x" RLOC = "X-21Y2" ;
INST "ADI_Clocking_inst/rx0/dout07d_x" RLOC = "X-22Y5" ;
INST "ADI_Clocking_inst/rx0/dout06d_x" RLOC = "X-22Y4" ;
INST "ADI_Clocking_inst/rx0/dout05d_x" RLOC = "X-23Y5" ;
INST "ADI_Clocking_inst/rx0/dout04d_x" RLOC = "X-23Y4" ;
INST "ADI_Clocking_inst/rx0/dout03d_x" RLOC = "X-22Y3" ;
INST "ADI_Clocking_inst/rx0/dout02d_x" RLOC = "X-22Y2" ;
INST "ADI_Clocking_inst/rx0/dout01d_x" RLOC = "X-24Y5" ;
INST "ADI_Clocking_inst/rx0/dout00d_x" RLOC = "X-24Y4" ;

INST "ADI_Clocking_inst/rx0/dout13c_x" RLOC = "X-21Y9" ;
INST "ADI_Clocking_inst/rx0/dout12c_x" RLOC = "X-21Y8" ;
INST "ADI_Clocking_inst/rx0/dout11c_x" RLOC = "X-20Y7" ;
INST "ADI_Clocking_inst/rx0/dout10c_x" RLOC = "X-20Y6" ;