JDF G
// Created by Project Navigator ver 1.0
PROJECT ADI_Deserializer_AD9289_RevD
DESIGN adi_deserializer_ad9289_revd
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v250
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 1075505510
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 1072120187
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE ADI_Top_RevD.v
SOURCE ADI_Clocking_RevD.v
SOURCE ADI_Shift_RevD.v
DEPASSOC ADI_Top_RevD ADI_Deserializer_AD9289_RevD.ucf
[Normal]
p_ChangeDevSpeed=xstvlg, virtex2, Verilog.t_postMapSimModel, 1075166806, -4
p_CompxlibTargetSimulator=xstvlg, virtex2, Design.t_compLibraries, 1072105991, ModelSim PE
p_impactBaud=xstvlg, virtex2, Implementation.t_impactProgrammingTool, 1072107127, Auto
p_impactConfigMode=xstvlg, virtex2, Implementation.t_impactProgrammingTool, 1072107127, Boundary Scan
p_impactPort=xstvlg, virtex2, Implementation.t_impactProgrammingTool, 1072107127, LPT 1 (PC)
p_MapEffortLevel=xstvlg, virtex2, Implementation.t_map, 1075166806, High
p_map_otherCmdLineOptions=xstvlg, virtex2, Implementation.t_map, 1076084290,
p_parGenAsyDlyRpt=xstvlg, virtex2, Implementation.t_par, 1076954784, True
p_parGenSimModel=xstvlg, virtex2, Implementation.t_par, 1072106290, True
p_PostTrceFastPath=xstvlg, virtex2, Implementation.t_postRouteTrce, 1076511692, True
p_xstEquivRegRemoval=xstvlg, virtex2, Schematic.t_synthesize, 1077222790, False
p_xstHierarchySeparator=xstvlg, virtex2, Schematic.t_synthesize, 1066018245, /
p_xstUseSynthConstFile=xstvlg, virtex2, Schematic.t_synthesize, 1077838692, False
xilxBitgStart_Clk=xstvlg, virtex2, Implementation.t_bitFile, 1076451038, JTAG Clock
xilxBitgStart_Clk_Done=xstvlg, virtex2, Implementation.t_bitFile, 1075734343, Default (4)
xilxBitgStart_Clk_EnOut=xstvlg, virtex2, Implementation.t_bitFile, 1075734343, Default (5)
xilxBitgStart_Clk_RelDLL=xstvlg, virtex2, Implementation.t_bitFile, 1075734343, Default (NoWait)
xilxBitgStart_Clk_WrtEn=xstvlg, virtex2, Implementation.t_bitFile, 1075734343, Default (6)
xilxMapCoverMode=xstvlg, virtex2, Implementation.t_map, 1077815051, Speed
xilxMapReportDetail=xstvlg, virtex2, Implementation.t_map, 1075152970, True
xilxMapTimingDrivenPacking=xstvlg, virtex2, Implementation.t_map, 1077822820, True
xilxPAReffortLevel=xstvlg, virtex2, Implementation.t_par, 1075166806, High
xilxPARextraEffortLevel=xstvlg, virtex2, Implementation.t_par, 1076954784, Normal
xilxPARrouterEffortLevel=xstvlg, virtex2, Implementation.t_par, 1077139611, None
xilxPostTrceRptLimit=xstvlg, virtex2, Implementation.t_postRouteTrce, 1076700766, 50
xilxPostTrceRptTiming=xstvlg, virtex2, Implementation.t_postRouteTrce, 1076700766, 50
xilxPreTrceAdvAna=xstvlg, virtex2, Implementation.t_preRouteTrce, 1076700766, True
xilxPreTrceRptLimit=xstvlg, virtex2, Implementation.t_preRouteTrce, 1076700766, 50
xilxPreTrceRptTiming=xstvlg, virtex2, Implementation.t_preRouteTrce, 1076700766, 50
xilxSynthMaxFanout=xstvlg, virtex2, Schematic.t_synthesize, 1077839158, 500
_SynthConstraintsFile=xstvlg, virtex2, Schematic.t_synthesize, 1077838373, C:\Data\projects\analog_devices\Mike_Hughes\adc12bit3b\2_20_04\GP_ADC_XST.xcf
_SynthOptEffort=xstvlg, virtex2, Schematic.t_synthesize, 1077815026, High
[STRATEGY-LIST]
Normal=True