module te(en,dat,out,clk);
input  [31:0]dat;
input   clk,en;
output out;
reg out;
always @(posedge clk)
   begin
   if(!en)
		out<=1'b0;
	else
		begin
		if(dat==492)
			out<=1'b1;
		end
	end

endmodule