--fifo
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;

entity blockdram is
generic( 
	depth:	integer;
	Dwidth: integer;
	Awidth:	integer
);
port(
	addra: IN std_logic_VECTOR(Awidth-1 downto 0);
	clka: IN std_logic;
	addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
	clkb: IN std_logic;
	dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
	wea: IN std_logic;	 
	rea: IN std_logic;
	dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
end blockdram;	
--port(
--	addra: IN std_logic_VECTOR(5 downto 0);
--	clka: IN std_logic;
--	addrb: IN std_logic_VECTOR(5 downto 0);
--	clkb: IN std_logic;
--	dia: IN std_logic_VECTOR(7 downto 0);
--	wea: IN std_logic;	 
--	rea: IN std_logic;
--	dob: OUT std_logic_VECTOR(7 downto 0));
--end blockdram;

architecture arch_blockdram of blockdram is

type ram_memtype is array (35 downto 0) of std_logic_vector
	(7 downto 0);
signal mem : ram_memtype:=(others=>(others=>'0'));
attribute syn_ramstyle of mem : signal is "block_ram";
signal addra_reg : integer range 0 to 35;
--signal addrb_reg: std_logic_vector(5 downto 0);
signal addrb_reg : integer range 0 to 35;

begin
addra_reg <= conv_integer(addra);	
	wr: process( clka )
	begin
		if rising_edge(clka) then
			if wea = '1' then
				mem(addra_reg) <= dia;
			--	mem(conv_integer(addra)) <= dia;
			end if;
		end if;
	end process wr;


	rd: process( clkb )
	begin
		if rising_edge(clkb) then	   
			if rea='1' then
				addrb_reg <= conv_integer(addrb);
			end if;
		end if;
    end process rd;
	dob <= mem(addrb_reg);
end arch_blockdram;