library IEEE;
use ieee.std_logic_1164.all;
 
entity cntshow is
port
(CLK,RST,EN : IN STD_LOGIC;
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  ;
COUT : OUT STD_LOGIC );
end cntshow;
architecture arch of cntshow is 
component decl7s is
port
(A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ;
end component;

component cnt12 is
port
(CLK,RST,EN : IN STD_LOGIC;
CQ : buffer STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC );
end component;

signal qa: std_logic_vector(3 downto 0);
begin
u1: cnt12 port map(CLK,RST,EN,qa,cout);
u2: decl7s port map(qa,led7s);
end arch;