?? singt.tan.rpt
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+-------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; CLK1 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg6 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg6 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg5 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg5 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg4 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg4 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg3 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg3 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg2 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg2 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg1 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg1 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg0 ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg0 ; CLK ; CLK ; None ; None ; 4.319 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[0] ; Q1[5] ; CLK ; CLK ; None ; None ; 2.260 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[0] ; Q1[4] ; CLK ; CLK ; None ; None ; 2.260 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[1] ; Q1[5] ; CLK ; CLK ; None ; None ; 2.201 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[1] ; Q1[4] ; CLK ; CLK ; None ; None ; 2.201 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[0] ; Q1[3] ; CLK ; CLK ; None ; None ; 2.045 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[1] ; Q1[3] ; CLK ; CLK ; None ; None ; 1.984 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[0] ; Q1[2] ; CLK ; CLK ; None ; None ; 1.965 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[2] ; Q1[5] ; CLK ; CLK ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[2] ; Q1[4] ; CLK ; CLK ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[3] ; Q1[5] ; CLK ; CLK ; None ; None ; 1.920 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[3] ; Q1[4] ; CLK ; CLK ; None ; None ; 1.920 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[3] ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 1.910 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q1[1] ; Q1[2] ; CLK ; CLK ; None ; None ; 1.904 ns ;
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