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--KB1_q_a[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[0]_PORT_A_data_in = VCC;
KB1_q_a[0]_PORT_A_data_in_reg = DFFE(KB1_q_a[0]_PORT_A_data_in, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_data_in = LB1_ram_rom_data_reg[0];
KB1_q_a[0]_PORT_B_data_in_reg = DFFE(KB1_q_a[0]_PORT_B_data_in, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[0]_PORT_A_address_reg = DFFE(KB1_q_a[0]_PORT_A_address, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[0]_PORT_B_address_reg = DFFE(KB1_q_a[0]_PORT_B_address, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_PORT_A_write_enable = GND;
KB1_q_a[0]_PORT_A_write_enable_reg = DFFE(KB1_q_a[0]_PORT_A_write_enable, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_write_enable = LB1L2;
KB1_q_a[0]_PORT_B_write_enable_reg = DFFE(KB1_q_a[0]_PORT_B_write_enable, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_clock_0 = CLK;
KB1_q_a[0]_clock_1 = A1L5;
KB1_q_a[0]_PORT_A_data_out = MEMORY(KB1_q_a[0]_PORT_A_data_in_reg, KB1_q_a[0]_PORT_B_data_in_reg, KB1_q_a[0]_PORT_A_address_reg, KB1_q_a[0]_PORT_B_address_reg, KB1_q_a[0]_PORT_A_write_enable_reg, KB1_q_a[0]_PORT_B_write_enable_reg, , , KB1_q_a[0]_clock_0, KB1_q_a[0]_clock_1, , , , );
KB1_q_a[0] = KB1_q_a[0]_PORT_A_data_out[0];

--KB1_q_b[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[0]
KB1_q_b[0]_PORT_A_data_in = VCC;
KB1_q_b[0]_PORT_A_data_in_reg = DFFE(KB1_q_b[0]_PORT_A_data_in, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_data_in = LB1_ram_rom_data_reg[0];
KB1_q_b[0]_PORT_B_data_in_reg = DFFE(KB1_q_b[0]_PORT_B_data_in, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[0]_PORT_A_address_reg = DFFE(KB1_q_b[0]_PORT_A_address, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[0]_PORT_B_address_reg = DFFE(KB1_q_b[0]_PORT_B_address, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_write_enable = GND;
KB1_q_b[0]_PORT_A_write_enable_reg = DFFE(KB1_q_b[0]_PORT_A_write_enable, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_write_enable = LB1L2;
KB1_q_b[0]_PORT_B_write_enable_reg = DFFE(KB1_q_b[0]_PORT_B_write_enable, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_clock_0 = CLK;
KB1_q_b[0]_clock_1 = A1L5;
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[0] = KB1_q_b[0]_PORT_B_data_out[0];


--KB1_q_a[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[1]_PORT_A_data_in = VCC;
KB1_q_a[1]_PORT_A_data_in_reg = DFFE(KB1_q_a[1]_PORT_A_data_in, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_data_in = LB1_ram_rom_data_reg[1];
KB1_q_a[1]_PORT_B_data_in_reg = DFFE(KB1_q_a[1]_PORT_B_data_in, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[1]_PORT_A_address_reg = DFFE(KB1_q_a[1]_PORT_A_address, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[1]_PORT_B_address_reg = DFFE(KB1_q_a[1]_PORT_B_address, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_PORT_A_write_enable = GND;
KB1_q_a[1]_PORT_A_write_enable_reg = DFFE(KB1_q_a[1]_PORT_A_write_enable, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_write_enable = LB1L2;
KB1_q_a[1]_PORT_B_write_enable_reg = DFFE(KB1_q_a[1]_PORT_B_write_enable, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_clock_0 = CLK;
KB1_q_a[1]_clock_1 = A1L5;
KB1_q_a[1]_PORT_A_data_out = MEMORY(KB1_q_a[1]_PORT_A_data_in_reg, KB1_q_a[1]_PORT_B_data_in_reg, KB1_q_a[1]_PORT_A_address_reg, KB1_q_a[1]_PORT_B_address_reg, KB1_q_a[1]_PORT_A_write_enable_reg, KB1_q_a[1]_PORT_B_write_enable_reg, , , KB1_q_a[1]_clock_0, KB1_q_a[1]_clock_1, , , , );
KB1_q_a[1] = KB1_q_a[1]_PORT_A_data_out[0];

--KB1_q_b[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[1]
KB1_q_b[1]_PORT_A_data_in = VCC;
KB1_q_b[1]_PORT_A_data_in_reg = DFFE(KB1_q_b[1]_PORT_A_data_in, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_data_in = LB1_ram_rom_data_reg[1];
KB1_q_b[1]_PORT_B_data_in_reg = DFFE(KB1_q_b[1]_PORT_B_data_in, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[1]_PORT_A_address_reg = DFFE(KB1_q_b[1]_PORT_A_address, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[1]_PORT_B_address_reg = DFFE(KB1_q_b[1]_PORT_B_address, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_PORT_A_write_enable = GND;
KB1_q_b[1]_PORT_A_write_enable_reg = DFFE(KB1_q_b[1]_PORT_A_write_enable, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_write_enable = LB1L2;
KB1_q_b[1]_PORT_B_write_enable_reg = DFFE(KB1_q_b[1]_PORT_B_write_enable, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_clock_0 = CLK;
KB1_q_b[1]_clock_1 = A1L5;
KB1_q_b[1]_PORT_B_data_out = MEMORY(KB1_q_b[1]_PORT_A_data_in_reg, KB1_q_b[1]_PORT_B_data_in_reg, KB1_q_b[1]_PORT_A_address_reg, KB1_q_b[1]_PORT_B_address_reg, KB1_q_b[1]_PORT_A_write_enable_reg, KB1_q_b[1]_PORT_B_write_enable_reg, , , KB1_q_b[1]_clock_0, KB1_q_b[1]_clock_1, , , , );
KB1_q_b[1] = KB1_q_b[1]_PORT_B_data_out[0];


--KB1_q_a[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[2]_PORT_A_data_in = VCC;
KB1_q_a[2]_PORT_A_data_in_reg = DFFE(KB1_q_a[2]_PORT_A_data_in, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_data_in = LB1_ram_rom_data_reg[2];
KB1_q_a[2]_PORT_B_data_in_reg = DFFE(KB1_q_a[2]_PORT_B_data_in, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[2]_PORT_A_address_reg = DFFE(KB1_q_a[2]_PORT_A_address, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[2]_PORT_B_address_reg = DFFE(KB1_q_a[2]_PORT_B_address, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_PORT_A_write_enable = GND;
KB1_q_a[2]_PORT_A_write_enable_reg = DFFE(KB1_q_a[2]_PORT_A_write_enable, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_write_enable = LB1L2;
KB1_q_a[2]_PORT_B_write_enable_reg = DFFE(KB1_q_a[2]_PORT_B_write_enable, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_clock_0 = CLK;
KB1_q_a[2]_clock_1 = A1L5;
KB1_q_a[2]_PORT_A_data_out = MEMORY(KB1_q_a[2]_PORT_A_data_in_reg, KB1_q_a[2]_PORT_B_data_in_reg, KB1_q_a[2]_PORT_A_address_reg, KB1_q_a[2]_PORT_B_address_reg, KB1_q_a[2]_PORT_A_write_enable_reg, KB1_q_a[2]_PORT_B_write_enable_reg, , , KB1_q_a[2]_clock_0, KB1_q_a[2]_clock_1, , , , );
KB1_q_a[2] = KB1_q_a[2]_PORT_A_data_out[0];

--KB1_q_b[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[2]
KB1_q_b[2]_PORT_A_data_in = VCC;
KB1_q_b[2]_PORT_A_data_in_reg = DFFE(KB1_q_b[2]_PORT_A_data_in, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_data_in = LB1_ram_rom_data_reg[2];
KB1_q_b[2]_PORT_B_data_in_reg = DFFE(KB1_q_b[2]_PORT_B_data_in, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[2]_PORT_A_address_reg = DFFE(KB1_q_b[2]_PORT_A_address, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[2]_PORT_B_address_reg = DFFE(KB1_q_b[2]_PORT_B_address, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_PORT_A_write_enable = GND;
KB1_q_b[2]_PORT_A_write_enable_reg = DFFE(KB1_q_b[2]_PORT_A_write_enable, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_write_enable = LB1L2;
KB1_q_b[2]_PORT_B_write_enable_reg = DFFE(KB1_q_b[2]_PORT_B_write_enable, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_clock_0 = CLK;
KB1_q_b[2]_clock_1 = A1L5;
KB1_q_b[2]_PORT_B_data_out = MEMORY(KB1_q_b[2]_PORT_A_data_in_reg, KB1_q_b[2]_PORT_B_data_in_reg, KB1_q_b[2]_PORT_A_address_reg, KB1_q_b[2]_PORT_B_address_reg, KB1_q_b[2]_PORT_A_write_enable_reg, KB1_q_b[2]_PORT_B_write_enable_reg, , , KB1_q_b[2]_clock_0, KB1_q_b[2]_clock_1, , , , );
KB1_q_b[2] = KB1_q_b[2]_PORT_B_data_out[0];


--KB1_q_a[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[3]_PORT_A_data_in = VCC;
KB1_q_a[3]_PORT_A_data_in_reg = DFFE(KB1_q_a[3]_PORT_A_data_in, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_data_in = LB1_ram_rom_data_reg[3];
KB1_q_a[3]_PORT_B_data_in_reg = DFFE(KB1_q_a[3]_PORT_B_data_in, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[3]_PORT_A_address_reg = DFFE(KB1_q_a[3]_PORT_A_address, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[3]_PORT_B_address_reg = DFFE(KB1_q_a[3]_PORT_B_address, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_PORT_A_write_enable = GND;
KB1_q_a[3]_PORT_A_write_enable_reg = DFFE(KB1_q_a[3]_PORT_A_write_enable, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_write_enable = LB1L2;
KB1_q_a[3]_PORT_B_write_enable_reg = DFFE(KB1_q_a[3]_PORT_B_write_enable, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_clock_0 = CLK;
KB1_q_a[3]_clock_1 = A1L5;
KB1_q_a[3]_PORT_A_data_out = MEMORY(KB1_q_a[3]_PORT_A_data_in_reg, KB1_q_a[3]_PORT_B_data_in_reg, KB1_q_a[3]_PORT_A_address_reg, KB1_q_a[3]_PORT_B_address_reg, KB1_q_a[3]_PORT_A_write_enable_reg, KB1_q_a[3]_PORT_B_write_enable_reg, , , KB1_q_a[3]_clock_0, KB1_q_a[3]_clock_1, , , , );
KB1_q_a[3] = KB1_q_a[3]_PORT_A_data_out[0];

--KB1_q_b[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[3]
KB1_q_b[3]_PORT_A_data_in = VCC;
KB1_q_b[3]_PORT_A_data_in_reg = DFFE(KB1_q_b[3]_PORT_A_data_in, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_data_in = LB1_ram_rom_data_reg[3];
KB1_q_b[3]_PORT_B_data_in_reg = DFFE(KB1_q_b[3]_PORT_B_data_in, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[3]_PORT_A_address_reg = DFFE(KB1_q_b[3]_PORT_A_address, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[3]_PORT_B_address_reg = DFFE(KB1_q_b[3]_PORT_B_address, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_PORT_A_write_enable = GND;
KB1_q_b[3]_PORT_A_write_enable_reg = DFFE(KB1_q_b[3]_PORT_A_write_enable, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_write_enable = LB1L2;
KB1_q_b[3]_PORT_B_write_enable_reg = DFFE(KB1_q_b[3]_PORT_B_write_enable, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_clock_0 = CLK;
KB1_q_b[3]_clock_1 = A1L5;
KB1_q_b[3]_PORT_B_data_out = MEMORY(KB1_q_b[3]_PORT_A_data_in_reg, KB1_q_b[3]_PORT_B_data_in_reg, KB1_q_b[3]_PORT_A_address_reg, KB1_q_b[3]_PORT_B_address_reg, KB1_q_b[3]_PORT_A_write_enable_reg, KB1_q_b[3]_PORT_B_write_enable_reg, , , KB1_q_b[3]_clock_0, KB1_q_b[3]_clock_1, , , , );
KB1_q_b[3] = KB1_q_b[3]_PORT_B_data_out[0];


--KB1_q_a[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[4]_PORT_A_data_in = VCC;
KB1_q_a[4]_PORT_A_data_in_reg = DFFE(KB1_q_a[4]_PORT_A_data_in, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_data_in = LB1_ram_rom_data_reg[4];
KB1_q_a[4]_PORT_B_data_in_reg = DFFE(KB1_q_a[4]_PORT_B_data_in, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[4]_PORT_A_address_reg = DFFE(KB1_q_a[4]_PORT_A_address, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[4]_PORT_B_address_reg = DFFE(KB1_q_a[4]_PORT_B_address, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_PORT_A_write_enable = GND;
KB1_q_a[4]_PORT_A_write_enable_reg = DFFE(KB1_q_a[4]_PORT_A_write_enable, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_write_enable = LB1L2;
KB1_q_a[4]_PORT_B_write_enable_reg = DFFE(KB1_q_a[4]_PORT_B_write_enable, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_clock_0 = CLK;
KB1_q_a[4]_clock_1 = A1L5;
KB1_q_a[4]_PORT_A_data_out = MEMORY(KB1_q_a[4]_PORT_A_data_in_reg, KB1_q_a[4]_PORT_B_data_in_reg, KB1_q_a[4]_PORT_A_address_reg, KB1_q_a[4]_PORT_B_address_reg, KB1_q_a[4]_PORT_A_write_enable_reg, KB1_q_a[4]_PORT_B_write_enable_reg, , , KB1_q_a[4]_clock_0, KB1_q_a[4]_clock_1, , , , );
KB1_q_a[4] = KB1_q_a[4]_PORT_A_data_out[0];

--KB1_q_b[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[4]
KB1_q_b[4]_PORT_A_data_in = VCC;
KB1_q_b[4]_PORT_A_data_in_reg = DFFE(KB1_q_b[4]_PORT_A_data_in, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_data_in = LB1_ram_rom_data_reg[4];
KB1_q_b[4]_PORT_B_data_in_reg = DFFE(KB1_q_b[4]_PORT_B_data_in, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[4]_PORT_A_address_reg = DFFE(KB1_q_b[4]_PORT_A_address, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[4]_PORT_B_address_reg = DFFE(KB1_q_b[4]_PORT_B_address, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_PORT_A_write_enable = GND;
KB1_q_b[4]_PORT_A_write_enable_reg = DFFE(KB1_q_b[4]_PORT_A_write_enable, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_write_enable = LB1L2;
KB1_q_b[4]_PORT_B_write_enable_reg = DFFE(KB1_q_b[4]_PORT_B_write_enable, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_clock_0 = CLK;
KB1_q_b[4]_clock_1 = A1L5;
KB1_q_b[4]_PORT_B_data_out = MEMORY(KB1_q_b[4]_PORT_A_data_in_reg, KB1_q_b[4]_PORT_B_data_in_reg, KB1_q_b[4]_PORT_A_address_reg, KB1_q_b[4]_PORT_B_address_reg, KB1_q_b[4]_PORT_A_write_enable_reg, KB1_q_b[4]_PORT_B_write_enable_reg, , , KB1_q_b[4]_clock_0, KB1_q_b[4]_clock_1, , , , );
KB1_q_b[4] = KB1_q_b[4]_PORT_B_data_out[0];


--KB1_q_a[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[5]_PORT_A_data_in = VCC;
KB1_q_a[5]_PORT_A_data_in_reg = DFFE(KB1_q_a[5]_PORT_A_data_in, KB1_q_a[5]_clock_0, , , );
KB1_q_a[5]_PORT_B_data_in = LB1_ram_rom_data_reg[5];
KB1_q_a[5]_PORT_B_data_in_reg = DFFE(KB1_q_a[5]_PORT_B_data_in, KB1_q_a[5]_clock_1, , , );
KB1_q_a[5]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[5]_PORT_A_address_reg = DFFE(KB1_q_a[5]_PORT_A_address, KB1_q_a[5]_clock_0, , , );
KB1_q_a[5]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[5]_PORT_B_address_reg = DFFE(KB1_q_a[5]_PORT_B_address, KB1_q_a[5]_clock_1, , , );
KB1_q_a[5]_PORT_A_write_enable = GND;
KB1_q_a[5]_PORT_A_write_enable_reg = DFFE(KB1_q_a[5]_PORT_A_write_enable, KB1_q_a[5]_clock_0, , , );
KB1_q_a[5]_PORT_B_write_enable = LB1L2;
KB1_q_a[5]_PORT_B_write_enable_reg = DFFE(KB1_q_a[5]_PORT_B_write_enable, KB1_q_a[5]_clock_1, , , );
KB1_q_a[5]_clock_0 = CLK;
KB1_q_a[5]_clock_1 = A1L5;
KB1_q_a[5]_PORT_A_data_out = MEMORY(KB1_q_a[5]_PORT_A_data_in_reg, KB1_q_a[5]_PORT_B_data_in_reg, KB1_q_a[5]_PORT_A_address_reg, KB1_q_a[5]_PORT_B_address_reg, KB1_q_a[5]_PORT_A_write_enable_reg, KB1_q_a[5]_PORT_B_write_enable_reg, , , KB1_q_a[5]_clock_0, KB1_q_a[5]_clock_1, , , , );
KB1_q_a[5] = KB1_q_a[5]_PORT_A_data_out[0];

--KB1_q_b[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[5]
KB1_q_b[5]_PORT_A_data_in = VCC;
KB1_q_b[5]_PORT_A_data_in_reg = DFFE(KB1_q_b[5]_PORT_A_data_in, KB1_q_b[5]_clock_0, , , );
KB1_q_b[5]_PORT_B_data_in = LB1_ram_rom_data_reg[5];
KB1_q_b[5]_PORT_B_data_in_reg = DFFE(KB1_q_b[5]_PORT_B_data_in, KB1_q_b[5]_clock_1, , , );
KB1_q_b[5]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[5]_PORT_A_address_reg = DFFE(KB1_q_b[5]_PORT_A_address, KB1_q_b[5]_clock_0, , , );
KB1_q_b[5]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[5]_PORT_B_address_reg = DFFE(KB1_q_b[5]_PORT_B_address, KB1_q_b[5]_clock_1, , , );
KB1_q_b[5]_PORT_A_write_enable = GND;
KB1_q_b[5]_PORT_A_write_enable_reg = DFFE(KB1_q_b[5]_PORT_A_write_enable, KB1_q_b[5]_clock_0, , , );
KB1_q_b[5]_PORT_B_write_enable = LB1L2;
KB1_q_b[5]_PORT_B_write_enable_reg = DFFE(KB1_q_b[5]_PORT_B_write_enable, KB1_q_b[5]_clock_1, , , );
KB1_q_b[5]_clock_0 = CLK;
KB1_q_b[5]_clock_1 = A1L5;
KB1_q_b[5]_PORT_B_data_out = MEMORY(KB1_q_b[5]_PORT_A_data_in_reg, KB1_q_b[5]_PORT_B_data_in_reg, KB1_q_b[5]_PORT_A_address_reg, KB1_q_b[5]_PORT_B_address_reg, KB1_q_b[5]_PORT_A_write_enable_reg, KB1_q_b[5]_PORT_B_write_enable_reg, , , KB1_q_b[5]_clock_0, KB1_q_b[5]_clock_1, , , , );
KB1_q_b[5] = KB1_q_b[5]_PORT_B_data_out[0];


--KB1_q_a[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[6]_PORT_A_data_in = VCC;
KB1_q_a[6]_PORT_A_data_in_reg = DFFE(KB1_q_a[6]_PORT_A_data_in, KB1_q_a[6]_clock_0, , , );
KB1_q_a[6]_PORT_B_data_in = LB1_ram_rom_data_reg[6];
KB1_q_a[6]_PORT_B_data_in_reg = DFFE(KB1_q_a[6]_PORT_B_data_in, KB1_q_a[6]_clock_1, , , );
KB1_q_a[6]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[6]_PORT_A_address_reg = DFFE(KB1_q_a[6]_PORT_A_address, KB1_q_a[6]_clock_0, , , );
KB1_q_a[6]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[6]_PORT_B_address_reg = DFFE(KB1_q_a[6]_PORT_B_address, KB1_q_a[6]_clock_1, , , );
KB1_q_a[6]_PORT_A_write_enable = GND;
KB1_q_a[6]_PORT_A_write_enable_reg = DFFE(KB1_q_a[6]_PORT_A_write_enable, KB1_q_a[6]_clock_0, , , );
KB1_q_a[6]_PORT_B_write_enable = LB1L2;
KB1_q_a[6]_PORT_B_write_enable_reg = DFFE(KB1_q_a[6]_PORT_B_write_enable, KB1_q_a[6]_clock_1, , , );
KB1_q_a[6]_clock_0 = CLK;
KB1_q_a[6]_clock_1 = A1L5;
KB1_q_a[6]_PORT_A_data_out = MEMORY(KB1_q_a[6]_PORT_A_data_in_reg, KB1_q_a[6]_PORT_B_data_in_reg, KB1_q_a[6]_PORT_A_address_reg, KB1_q_a[6]_PORT_B_address_reg, KB1_q_a[6]_PORT_A_write_enable_reg, KB1_q_a[6]_PORT_B_write_enable_reg, , , KB1_q_a[6]_clock_0, KB1_q_a[6]_clock_1, , , , );