?? singt.fit.eqn
字號:
KB1_q_b[0]_clock_1 = GLOBAL(A1L5);
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[4] = KB1_q_b[0]_PORT_B_data_out[4];
--KB1_q_b[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[3] at M4K_X13_Y7
KB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_b[0]_PORT_A_data_in_reg = DFFE(KB1_q_b[0]_PORT_A_data_in, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[0], LB1_ram_rom_data_reg[1], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[7]);
KB1_q_b[0]_PORT_B_data_in_reg = DFFE(KB1_q_b[0]_PORT_B_data_in, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[0]_PORT_A_address_reg = DFFE(KB1_q_b[0]_PORT_A_address, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[0]_PORT_B_address_reg = DFFE(KB1_q_b[0]_PORT_B_address, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_write_enable = GND;
KB1_q_b[0]_PORT_A_write_enable_reg = DFFE(KB1_q_b[0]_PORT_A_write_enable, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_write_enable = LB1L2;
KB1_q_b[0]_PORT_B_write_enable_reg = DFFE(KB1_q_b[0]_PORT_B_write_enable, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_clock_0 = GLOBAL(CLK);
KB1_q_b[0]_clock_1 = GLOBAL(A1L5);
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[3] = KB1_q_b[0]_PORT_B_data_out[3];
--KB1_q_b[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[2] at M4K_X13_Y7
KB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_b[0]_PORT_A_data_in_reg = DFFE(KB1_q_b[0]_PORT_A_data_in, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[0], LB1_ram_rom_data_reg[1], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[7]);
KB1_q_b[0]_PORT_B_data_in_reg = DFFE(KB1_q_b[0]_PORT_B_data_in, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[0]_PORT_A_address_reg = DFFE(KB1_q_b[0]_PORT_A_address, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[0]_PORT_B_address_reg = DFFE(KB1_q_b[0]_PORT_B_address, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_write_enable = GND;
KB1_q_b[0]_PORT_A_write_enable_reg = DFFE(KB1_q_b[0]_PORT_A_write_enable, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_write_enable = LB1L2;
KB1_q_b[0]_PORT_B_write_enable_reg = DFFE(KB1_q_b[0]_PORT_B_write_enable, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_clock_0 = GLOBAL(CLK);
KB1_q_b[0]_clock_1 = GLOBAL(A1L5);
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[2] = KB1_q_b[0]_PORT_B_data_out[2];
--KB1_q_b[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[1] at M4K_X13_Y7
KB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_b[0]_PORT_A_data_in_reg = DFFE(KB1_q_b[0]_PORT_A_data_in, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[0], LB1_ram_rom_data_reg[1], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[7]);
KB1_q_b[0]_PORT_B_data_in_reg = DFFE(KB1_q_b[0]_PORT_B_data_in, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[0]_PORT_A_address_reg = DFFE(KB1_q_b[0]_PORT_A_address, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[0]_PORT_B_address_reg = DFFE(KB1_q_b[0]_PORT_B_address, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_write_enable = GND;
KB1_q_b[0]_PORT_A_write_enable_reg = DFFE(KB1_q_b[0]_PORT_A_write_enable, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_write_enable = LB1L2;
KB1_q_b[0]_PORT_B_write_enable_reg = DFFE(KB1_q_b[0]_PORT_B_write_enable, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_clock_0 = GLOBAL(CLK);
KB1_q_b[0]_clock_1 = GLOBAL(A1L5);
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[1] = KB1_q_b[0]_PORT_B_data_out[1];
--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);
--GB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X12_Y9_N6
--operation mode is normal
GB1_state[5] = AMPP_FUNCTION(A1L5, A1L7, GB1_state[4], GB1_state[3], VCC);
--EB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X12_Y8_N7
--operation mode is normal
EB5_Q[2] = AMPP_FUNCTION(A1L5, EB2_Q[0], EB7_Q[2], EB3_Q[2], C1_CLRN_SIGNAL, C1L24);
--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X10_Y8_N7
--operation mode is normal
C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, GB1_state[15], C1L31, C1_jtag_debug_mode, C1L30, GB1_state[0]);
--EB8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X11_Y8_N3
--operation mode is normal
EB8_Q[0] = AMPP_FUNCTION(A1L5, EB3_Q[8], altera_internal_jtag, C1_CLRN_SIGNAL, C1L22);
--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X18_Y8_N3
--operation mode is normal
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L43, A1L44, L5_dffs[0], L5_dffs[1], GB1_state[0], GB1_state[12]);
--EB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X17_Y6_N2
--operation mode is normal
EB2_Q[0] = AMPP_FUNCTION(A1L5, EB2_Q[0], HB1_dffe1a[1], EB9_Q[0], C1L1, C1_CLRN_SIGNAL);
--LB1L56 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~21 at LC_X11_Y8_N1
--operation mode is normal
LB1L56 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, EB2_Q[0], EB8_Q[0], C1_jtag_debug_mode);
--LB1L2 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X11_Y8_N4
--operation mode is normal
LB1L2 = AMPP_FUNCTION(GB1_state[5], EB5_Q[2], LB1L56);
--Q1[0] is Q1[0] at LC_X12_Y7_N1
--operation mode is arithmetic
Q1[0]_lut_out = !Q1[0];
Q1[0] = DFFEAS(Q1[0]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--A1L27 is Q1[0]~43 at LC_X12_Y7_N1
--operation mode is arithmetic
A1L27_cout_0 = Q1[0];
A1L27 = CARRY(A1L27_cout_0);
--A1L28 is Q1[0]~43COUT1_67 at LC_X12_Y7_N1
--operation mode is arithmetic
A1L28_cout_1 = Q1[0];
A1L28 = CARRY(A1L28_cout_1);
--Q1[1] is Q1[1] at LC_X12_Y7_N2
--operation mode is arithmetic
Q1[1]_lut_out = Q1[1] $ (A1L27);
Q1[1] = DFFEAS(Q1[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--A1L30 is Q1[1]~47 at LC_X12_Y7_N2
--operation mode is arithmetic
A1L30_cout_0 = !A1L27 # !Q1[1];
A1L30 = CARRY(A1L30_cout_0);
--A1L31 is Q1[1]~47COUT1_68 at LC_X12_Y7_N2
--operation mode is arithmetic
A1L31_cout_1 = !A1L28 # !Q1[1];
A1L31 = CARRY(A1L31_cout_1);
--Q1[2] is Q1[2] at LC_X12_Y7_N3
--operation mode is arithmetic
Q1[2]_lut_out = Q1[2] $ !A1L30;
Q1[2] = DFFEAS(Q1[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--A1L33 is Q1[2]~51 at LC_X12_Y7_N3
--operation mode is arithmetic
A1L33_cout_0 = Q1[2] & !A1L30;
A1L33 = CARRY(A1L33_cout_0);
--A1L34 is Q1[2]~51COUT1 at LC_X12_Y7_N3
--operation mode is arithmetic
A1L34_cout_1 = Q1[2] & !A1L31;
A1L34 = CARRY(A1L34_cout_1);
--Q1[3] is Q1[3] at LC_X12_Y7_N4
--operation mode is arithmetic
Q1[3]_lut_out = Q1[3] $ A1L33;
Q1[3] = DFFEAS(Q1[3]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--A1L36 is Q1[3]~55 at LC_X12_Y7_N4
--operation mode is arithmetic
A1L36 = A1L37;
--Q1[4] is Q1[4] at LC_X12_Y7_N5
--operation mode is arithmetic
Q1[4]_carry_eqn = (!A1L36 & GND) # (A1L36 & VCC);
Q1[4]_lut_out = Q1[4] $ !Q1[4]_carry_eqn;
Q1[4] = DFFEAS(Q1[4]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--A1L40 is Q1[4]~59 at LC_X12_Y7_N5
--operation mode is arithmetic
A1L40_cout_0 = Q1[4] & !A1L36;
A1L40 = CARRY(A1L40_cout_0);
--A1L41 is Q1[4]~59COUT1_69 at LC_X12_Y7_N5
--operation mode is arithmetic
A1L41_cout_1 = Q1[4] & !A1L36;
A1L41 = CARRY(A1L41_cout_1);
--Q1[5] is Q1[5] at LC_X12_Y7_N6
--operation mode is normal
Q1[5]_carry_eqn = (!A1L36 & A1L40) # (A1L36 & A1L41);
Q1[5]_lut_out = Q1[5] $ Q1[5]_carry_eqn;
Q1[5] = DFFEAS(Q1[5]_lut_out, GLOBAL(CLK), VCC, , , , , , );
--LB1_ram_rom_data_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LC_X12_Y8_N4
--operation mode is normal
LB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, KB1_q_b[0], LB1L11, LB1_ram_rom_data_reg[1], VCC, LB1L42);
--LB1_ram_rom_addr_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] at LC_X11_Y7_N1
--operation mode is arithmetic
LB1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[0], LB1_ram_rom_incr_addr, LB1_ram_rom_addr_reg[1], !EB5_Q[0], LB1L10);
--LB1L17 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~91 at LC_X11_Y7_N1
--operation mode is arithmetic
LB1L17 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[0], LB1_ram_rom_incr_addr);
--LB1L18 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~91COUT1_115 at LC_X11_Y7_N1
--operation mode is arithmetic
LB1L18 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[0], LB1_ram_rom_incr_addr);
--LB1_ram_rom_addr_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1] at LC_X11_Y7_N2
--operation mode is arithmetic
LB1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], !EB5_Q[0], LB1L10, LB1L17, LB1L18);
--LB1L20 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~95 at LC_X11_Y7_N2
--operation mode is arithmetic
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