L5_dffs[6] = AMPP_FUNCTION(A1L5, L5_dffs[7], GB1_state[0], GB1_state[11]);


--A1L43 is rtl~93 at LC_X15_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[9]_qfbk = L5_dffs[9];
A1L43 = !L5_dffs[6] & !L5_dffs[8] & !L5_dffs[9]_qfbk & !L5_dffs[7];

--L5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X15_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, GB1_state[0], GND, GB1_state[11]);


--L5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] at LC_X15_Y8_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[2] = AMPP_FUNCTION(A1L5, L5_dffs[3], GB1_state[0], GND, GB1_state[11]);


--L5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] at LC_X15_Y8_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[5] = AMPP_FUNCTION(A1L5, L5_dffs[6], GB1_state[0], GND, GB1_state[11]);


--L5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] at LC_X15_Y8_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[4] = AMPP_FUNCTION(A1L5, L5_dffs[5], GB1_state[0], GND, GB1_state[11]);


--A1L44 is rtl~94 at LC_X15_Y8_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[3]_qfbk = L5_dffs[3];
A1L44 = !L5_dffs[5] & L5_dffs[2] & L5_dffs[3]_qfbk & !L5_dffs[4];

--L5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] at LC_X15_Y8_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[3] = AMPP_FUNCTION(A1L5, L5_dffs[4], GB1_state[0], GND, GB1_state[11]);


--L5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] at LC_X9_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[0] = AMPP_FUNCTION(A1L5, L5_dffs[1], GB1_state[0], GND, GB1_state[11]);


--HB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] at LC_X15_Y7_N9
--operation mode is normal

HB1_dffe1a[1] = AMPP_FUNCTION(A1L5, EB3_Q[1], EB3_Q[2], EB3_Q[3], C1L30, C1_CLRN_SIGNAL, C1L5);


--GB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X20_Y8_N4
--operation mode is normal

GB1_state[8] = AMPP_FUNCTION(A1L5, GB1_state[5], GB1_state[7], VCC, !A1L7);


--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28 at LC_X15_Y7_N3
--operation mode is normal

C1L1 = AMPP_FUNCTION(GB1_state[8], C1_OK_TO_UPDATE_IR_Q, HB1_dffe1a[1], HB1_dffe1a[2]);


--EB5_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] at LC_X11_Y7_N8
--operation mode is normal

EB5_Q[3] = AMPP_FUNCTION(A1L5, EB2_Q[0], EB7_Q[3], EB3_Q[3], C1_CLRN_SIGNAL, C1L24);


--LB1_ram_rom_data_shift_cntr_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] at LC_X12_Y9_N2
--operation mode is arithmetic

LB1_ram_rom_data_shift_cntr_reg[1] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_shift_cntr_reg[1], !EB5_Q[3], LB1L57, LB1L45, LB1L46);

--LB1L48 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]~51 at LC_X12_Y9_N2
--operation mode is arithmetic

LB1L48 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[1], LB1L45);

--LB1L49 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]~51COUT1 at LC_X12_Y9_N2
--operation mode is arithmetic

LB1L49 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[1], LB1L46);


--EB5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X12_Y8_N5
--operation mode is normal

EB5_Q[1] = AMPP_FUNCTION(A1L5, EB3_Q[1], EB7_Q[1], EB2_Q[0], C1_CLRN_SIGNAL, C1L24);


--LB1_ram_rom_data_shift_cntr_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] at LC_X12_Y9_N1
--operation mode is arithmetic

LB1_ram_rom_data_shift_cntr_reg[0] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_shift_cntr_reg[0], LB1L12, !EB5_Q[3], LB1L57);

--LB1L45 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~55 at LC_X12_Y9_N1
--operation mode is arithmetic

LB1L45 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[0], LB1L12);

--LB1L46 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~55COUT1_67 at LC_X12_Y9_N1
--operation mode is arithmetic

LB1L46 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[0], LB1L12);


--LB1_ram_rom_data_shift_cntr_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] at LC_X12_Y9_N3
--operation mode is arithmetic

LB1_ram_rom_data_shift_cntr_reg[2] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_shift_cntr_reg[2], !EB5_Q[3], LB1L57, LB1L48, LB1L49);

--LB1L51 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]~59 at LC_X12_Y9_N3
--operation mode is arithmetic

LB1L51 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[2], LB1L48);

--LB1L52 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]~59COUT1_68 at LC_X12_Y9_N3
--operation mode is arithmetic

LB1L52 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[2], LB1L49);


--LB1_ram_rom_data_shift_cntr_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3] at LC_X12_Y9_N4
--operation mode is normal

LB1_ram_rom_data_shift_cntr_reg[3] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_shift_cntr_reg[3], !EB5_Q[3], LB1L57, LB1L51, LB1L52);


--LB1L58 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|rtl~26 at LC_X12_Y8_N0
--operation mode is normal

LB1L58 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[2], LB1_ram_rom_data_shift_cntr_reg[3], LB1_ram_rom_data_shift_cntr_reg[0]);


--LB1L11 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1 at LC_X12_Y8_N9
--operation mode is normal

LB1L11 = AMPP_FUNCTION(LB1_ram_rom_data_shift_cntr_reg[1], EB5_Q[1], EB5_Q[3], LB1L58);


--EB5L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~61 at LC_X12_Y8_N8
--operation mode is normal

EB5L4 = AMPP_FUNCTION(EB5_Q[2], EB5_Q[1]);


--LB1L42 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]~653 at LC_X12_Y8_N6
--operation mode is normal

LB1L42 = AMPP_FUNCTION(GB1_state[4], EB5L4, LB1L11, LB1L56);


--LB1L55 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~0 at LC_X12_Y8_N3
--operation mode is normal

LB1L55 = AMPP_FUNCTION(EB5_Q[1], LB1_ram_rom_data_shift_cntr_reg[1], LB1L58);


--LB1_ram_rom_incr_addr is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr at LC_X12_Y8_N1
--operation mode is normal

LB1_ram_rom_incr_addr = AMPP_FUNCTION(LB1L56, LB1L55, EB5_Q[2], GB1_state[8]);


--EB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] at LC_X12_Y6_N6
--operation mode is normal

EB5_Q[0] = AMPP_FUNCTION(A1L5, EB2_Q[0], EB7_Q[0], EB3_Q[0], C1_CLRN_SIGNAL, C1L24);


--LB1L10 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~12 at LC_X11_Y7_N7
--operation mode is normal

LB1L10 = AMPP_FUNCTION(GB1_state[4], EB5_Q[3], LB1L56);


--LB1L9 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 at LC_X16_Y8_N5
--operation mode is normal

LB1L9 = AMPP_FUNCTION(GB1_state[3], GB1_state[4], C1_jtag_debug_mode_usr1);


--G1_WORD_SR[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] at LC_X20_Y6_N4
--operation mode is normal

G1_WORD_SR[0] = AMPP_FUNCTION(A1L5, G1_word_counter[4], G2L15, G1L26, G1L27, VCC, G1L22);


--LB1_bypass_reg_out is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out at LC_X17_Y5_N3
--operation mode is normal

LB1_bypass_reg_out = AMPP_FUNCTION(A1L5, C1L32, altera_internal_jtag, LB1_bypass_reg_out, C1_CLRN_SIGNAL);


--C1L11 is sld_hub:sld_hub_inst|hub_tdo~808 at LC_X16_Y8_N9
--operation mode is normal

C1L11 = AMPP_FUNCTION(LB1_bypass_reg_out, EB5L4, G1_WORD_SR[0], EB5_Q[0]);


--C1L12 is sld_hub:sld_hub_inst|hub_tdo~809 at LC_X12_Y8_N2
--operation mode is normal

C1L12 = AMPP_FUNCTION(EB5_Q[2], EB5_Q[1], LB1_ram_rom_data_reg[0], EB5_Q[0]);


--C1L13 is sld_hub:sld_hub_inst|hub_tdo~810 at LC_X16_Y8_N8
--operation mode is normal

C1L13 = AMPP_FUNCTION(C1L11, LB1L9, C1L12, EB8_Q[0]);


--EB3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X17_Y8_N4
--operation mode is normal

EB3_Q[0] = AMPP_FUNCTION(A1L5, H1L5, C1L21, EB3_Q[1], LB1_is_in_use_reg, C1_CLRN_SIGNAL, GB1_state[4], EB3L4);


--GB1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 at LC_X16_Y8_N3
--operation mode is normal

GB1L18 = AMPP_FUNCTION(GB1_state[3], GB1_state[4]);


--C1L14 is sld_hub:sld_hub_inst|hub_tdo~811 at LC_X16_Y8_N6
--operation mode is normal

C1L14 = AMPP_FUNCTION(C1_hub_tdo, GB1L18, C1_jtag_debug_mode_usr1, EB3_Q[0]);


--G3_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] at LC_X20_Y8_N7
--operation mode is normal