Library IEEE;
Use IEEE.std_logic_1164.all;

Entity test2 is 
     port ( xi,clock,reset :in BIT;
		   zo :out BIT);
End test2;

Architecture behav of test2 is
     type state_type is (A, B, C, D, E, F, G, H);
     signal present_state, next_state : state_type;
Begin
  seq: process (clock,reset) is 
     begin
            if (reset='1') then	present_state<=A;
	    elsif  (clock'event and clock='1')  then
				present_state <= next_state;
            end if ;
      end process seq ;

  com: process ( xi, present_state ) 
     begin
			zo <= '0';
			case present_state is
                 when A =>
                 if ( xi = '1' ) then
                        next_state<=B;
                 else
                        next_state<=A;
				 end if;
				 when B =>
                 if ( xi = '1' ) then
                        next_state<=C;
                 else
                        next_state<=A;
				 end if;
				 when C =>
                 if ( xi = '1' ) then
                        next_state<=D;
                 else
                        next_state<=A;
				 end if;
				 when D =>
                 if ( xi = '0' ) then
                        next_state<=E;
                 else
                        next_state<=D;
				 end if;
				 when E =>
                 if ( xi = '0' ) then
                        next_state<=F;
                 else
                        next_state<=A;
				 end if;
				 when F =>
                 if ( xi = '1' ) then
                        next_state<=G;
                 else
                        next_state<=B;
				 end if;
				 when G =>
                 if ( xi = '0' ) then
                        next_state<=H;
                 else
                        next_state<=C;
				 end if;
				 when H =>
						zo <= '1';
                 if ( xi = '1' ) then
                        next_state<=B;
                 else
                        next_state<=A;
                 end if ;
			end case;
	End process com;
End behav;