?? lin.tan.rpt
字號:
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[20] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[19] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[18] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[17] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[16] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[7] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[6] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[5] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[4] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[3] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[2] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[1] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[0] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[0] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[7] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[6] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[5] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[4] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[3] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[2] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count[1] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[14] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[13] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[12] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[11] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[10] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[9] ; count1[5] ; clock ; clock ; None ; None ; None ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; count1[8] ; count1[5] ; clock ; clock ; None ; None ; None ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A ; None ; 5.000 ns ; pwm~reg0 ; pwm ; clock ;
+-------+--------------+------------+----------+-----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Fri Feb 24 00:05:53 2006
Info: Command: quartus_tan --import_settings_files=on --export_settings_files=off lin -c lin
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clock is an undefined clock
Info: Clock clock has Internal fmax of 55.56 MHz between source register count[1] and destination register count1[11] (period= 18.0 ns)
Info: + Longest register to register delay is 14.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 55; REG Node = 'count[1]'
Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC21; Fanout = 10; COMB Node = 'lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102'
Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC15; Fanout = 23; REG Node = 'count1[11]'
Info: Total cell delay = 12.000 ns ( 85.71 % )
Info: Total interconnect delay = 2.000 ns ( 14.29 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clock to destination register is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC15; Fanout = 23; REG Node = 'count1[11]'
Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: - Longest clock path from clock clock to source register is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC5; Fanout = 55; REG Node = 'count[1]'
Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 2.000 ns
Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock clock to destination pin pwm through register pwm~reg0 is 5.000 ns
Info: + Longest clock path from clock clock to source register is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC83; Fanout = 1; REG Node = 'pwm~reg0'
Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 2.000 ns
Info: + Longest register to pin delay is 1.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC83; Fanout = 1; REG Node = 'pwm~reg0'
Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'pwm'
Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Feb 24 00:05:54 2006
Info: Elapsed time: 00:00:00
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