?? ddsfpga.map.rpt
字號:
; altram.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_88s.tdf ; yes ; Auto-Generated Megafunction ; E:/creat/altera/DDS/DDSFPGA/db/altsyncram_88s.tdf ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+
+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+--------------------+
; Resource ; Usage ;
+-----------------------------------+--------------------+
; Total logic elements ; 323 ;
; Total combinational functions ; 302 ;
; -- Total 4-input functions ; 68 ;
; -- Total 3-input functions ; 22 ;
; -- Total 2-input functions ; 94 ;
; -- Total 1-input functions ; 118 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 127 ;
; Total logic cells in carry chains ; 191 ;
; I/O pins ; 57 ;
; Total memory bits ; 8192 ;
; Maximum fan-out node ; clock_d2:inst|clk2 ;
; Maximum fan-out ; 135 ;
; Total fan-out ; 1315 ;
; Average fan-out ; 3.39 ;
+-----------------------------------+--------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------------------+
; |DDSFPGA ; 323 (1) ; 127 ; 8192 ; 57 ; 0 ; 196 (1) ; 21 (0) ; 106 (0) ; 191 (0) ; |DDSFPGA ;
; |Key:inst3| ; 38 (38) ; 25 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 25 (25) ; 18 (18) ; |DDSFPGA|Key:inst3 ;
; |clock_d2:inst| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |DDSFPGA|clock_d2:inst ;
; |control:inst1| ; 264 (264) ; 84 ; 0 ; 0 ; 0 ; 180 (180) ; 20 (20) ; 64 (64) ; 173 (173) ; |DDSFPGA|control:inst1 ;
; |datachoose:inst2| ; 10 (10) ; 8 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; 0 (0) ; |DDSFPGA|datachoose:inst2 ;
; |romlookup:inst4| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDSFPGA|romlookup:inst4 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDSFPGA|romlookup:inst4|altsyncram:altsyncram_component ;
; |altsyncram_88s:auto_generated| ; 0 (0) ; 0 ; 8192 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDSFPGA|romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated ;
; |squwave:inst5| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |DDSFPGA|squwave:inst5 ;
; |triawave:inst6| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |DDSFPGA|triawave:inst6 ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
; romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated|ALTSYNCRAM ; M4K ; ROM ; 1024 ; 8 ; -- ; -- ; 8192 ; 1024.mif ;
+------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+----------+
+--------------------------------------------------------------------------------+
; State Machine - |DDSFPGA|control:inst1|state_wave ;
+---------------------+----------------+---------------------+-------------------+
; Name ; state_wave.sin ; state_wave.triangle ; state_wave.square ;
+---------------------+----------------+---------------------+-------------------+
; state_wave.square ; 0 ; 0 ; 0 ;
; state_wave.triangle ; 0 ; 1 ; 1 ;
; state_wave.sin ; 1 ; 0 ; 1 ;
+---------------------+----------------+---------------------+-------------------+
+-------------------------------------------------------------------------------------+
; State Machine - |DDSFPGA|control:inst1|state_adjust ;
+---------------------+---------------------+---------------------+-------------------+
; Name ; state_adjust.adj10k ; state_adjust.adj100 ; state_adjust.adj1 ;
+---------------------+---------------------+---------------------+-------------------+
; state_adjust.adj10k ; 0 ; 0 ; 0 ;
; state_adjust.adj100 ; 1 ; 1 ; 0 ;
; state_adjust.adj1 ; 1 ; 0 ; 1 ;
+---------------------+---------------------+---------------------+-------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 127 ;
; Number of registers using Synchronous Clear ; 16 ;
; Number of registers using Synchronous Load ; 36 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 108 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |DDSFPGA|control:inst1|DLedout[0] ;
; 3:1 ; 17 bits ; 34 LEs ; 0 LEs ; 34 LEs ; Yes ; |DDSFPGA|Key:inst3|scan[15] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DDSFPGA|Key:inst3|nkeyout[7] ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |DDSFPGA|triawave:inst6|qtriangle[7] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |DDSFPGA|datachoose:inst2|dataout[2] ;
; 12:1 ; 28 bits ; 224 LEs ; 112 LEs ; 112 LEs ; Yes ; |DDSFPGA|control:inst1|length[28] ;
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |DDSFPGA|control:inst1|state_wave~0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: control:inst1 ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------+
; square ; 001 ; Binary ;
; triangle ; 010 ; Binary ;
; sin ; 100 ; Binary ;
; adj1 ; 001 ; Binary ;
; adj100 ; 010 ; Binary ;
; adj10k ; 100 ; Binary ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: Key:inst3 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; n ; 10 ; Untyped ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: romlookup:inst4|altsyncram:altsyncram_component ;
+------------------------------------+----------------+----------------------------------------+
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