// Produced by /usr/class/ee272/bin/snoopgen from file chip.in// Remember to run Verilog with -x if any variables are subscripted// 2 Clock phases: phi1 phi2// Input, Verilog: external_y_s1, irsim: external_y_s1, vector[1:0]// Input, Verilog: self_test_s1, irsim: self_test_s1// Input, Verilog: sync_s1, irsim: sync_s1// Input, Verilog: phi2, irsim: phi2// Input, Verilog: phi1, irsim: phi1// Output, Verilog: path_metrics_s1, irsim: path_metrics_s1, vector[15:0], Stable phase 1// Output, Verilog: decisions_s1, irsim: decisions_s1, vector[3:0], Stable phase 1// Output, Verilog: decoded_column_s1, irsim: decoded_column_s1, vector[3:0], Stable phase 1// Output, Verilog: decoded_bit_s1, irsim: decoded_bit_s1, Stable phase 1// Output, Verilog: data_valid_s1, irsim: data_valid_s1, Stable phase 1// Output, Verilog: fail_s1, irsim: fail_s1, Stable phase 1// Output, Verilog: orig_del_bit_s1, irsim: orig_del_bit_s1, Stable phase 1module snooper(	phi1, phi2, sync_s1, self_test_s1, 	external_y_s1, orig_del_bit_s1, fail_s1, data_valid_s1, 	decoded_bit_s1, decoded_column_s1, decisions_s1, path_metrics_s1);input phi1;input phi2;input sync_s1;input self_test_s1;input [1:0] external_y_s1;input orig_del_bit_s1;input fail_s1;input data_valid_s1;input decoded_bit_s1;input [3:0] decoded_column_s1;input [3:0] decisions_s1;input [15:0] path_metrics_s1;initialbegin	$rsim_init();	$rsim_check_on();end// One always block per inputalways @(external_y_s1)begin	$rsim_log_input(external_y_s1[1], "external_y_s1[1]");	$rsim_log_input(external_y_s1[0], "external_y_s1[0]");endalways @(self_test_s1) $rsim_log_input(self_test_s1, "self_test_s1");always @(sync_s1) $rsim_log_input(sync_s1, "sync_s1");always @(phi2) $rsim_log_input(phi2, "phi2");always @(phi1) $rsim_log_input(phi1, "phi1");// One always block per inout// Let go of inouts// Check stable signalsalways @(phi1)begin	$rsim_log_output(path_metrics_s1[15], "path_metrics_s1[15]");	$rsim_log_output(path_metrics_s1[14], "path_metrics_s1[14]");	$rsim_log_output(path_metrics_s1[13], "path_metrics_s1[13]");	$rsim_log_output(path_metrics_s1[12], "path_metrics_s1[12]");	$rsim_log_output(path_metrics_s1[11], "path_metrics_s1[11]");	$rsim_log_output(path_metrics_s1[10], "path_metrics_s1[10]");	$rsim_log_output(path_metrics_s1[9], "path_metrics_s1[9]");	$rsim_log_output(path_metrics_s1[8], "path_metrics_s1[8]");	$rsim_log_output(path_metrics_s1[7], "path_metrics_s1[7]");	$rsim_log_output(path_metrics_s1[6], "path_metrics_s1[6]");	$rsim_log_output(path_metrics_s1[5], "path_metrics_s1[5]");	$rsim_log_output(path_metrics_s1[4], "path_metrics_s1[4]");	$rsim_log_output(path_metrics_s1[3], "path_metrics_s1[3]");	$rsim_log_output(path_metrics_s1[2], "path_metrics_s1[2]");	$rsim_log_output(path_metrics_s1[1], "path_metrics_s1[1]");	$rsim_log_output(path_metrics_s1[0], "path_metrics_s1[0]");	$rsim_log_output(decisions_s1[3], "decisions_s1[3]");	$rsim_log_output(decisions_s1[2], "decisions_s1[2]");	$rsim_log_output(decisions_s1[1], "decisions_s1[1]");	$rsim_log_output(decisions_s1[0], "decisions_s1[0]");	$rsim_log_output(decoded_column_s1[3], "decoded_column_s1[3]");	$rsim_log_output(decoded_column_s1[2], "decoded_column_s1[2]");	$rsim_log_output(decoded_column_s1[1], "decoded_column_s1[1]");	$rsim_log_output(decoded_column_s1[0], "decoded_column_s1[0]");	$rsim_log_output(decoded_bit_s1, "decoded_bit_s1");	$rsim_log_output(data_valid_s1, "data_valid_s1");	$rsim_log_output(fail_s1, "fail_s1");	$rsim_log_output(orig_del_bit_s1, "orig_del_bit_s1");endalways @(phi2)beginend// Check valid signalsalways @(negedge phi1)beginendalways @(negedge phi2)beginend// Check qualified signalsalways @(phi1)beginendalways @(phi2)beginendendmodule