A1L78Q_reg_input = !(A1L78Q_or_out);
A1L78Q = DFFE(A1L78Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[2] is readData_reg[2]
readData_reg[2]_p0_out = !readData_reg[1] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[2];
readData_reg[2]_p1_out = readData_reg[1] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[2];
readData_reg[2]_p2_out = !readData_reg[1] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[2] & A1L86Q;
readData_reg[2]_p3_out = !readData_reg[1] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[2] & A1L76Q;
readData_reg[2]_p4_out = !readData_reg[1] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[2] & !A1L86Q & !A1L76Q;
readData_reg[2]_or_out = A1L301 # readData_reg[2]_p0_out # readData_reg[2]_p1_out # readData_reg[2]_p2_out # readData_reg[2]_p3_out # readData_reg[2]_p4_out;
readData_reg[2]_reg_input = readData_reg[2]_or_out;
readData_reg[2] = TFFE(readData_reg[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L141Q is scl~reg0
A1L141Q_p1_out = A1L141Q & !phase2;
A1L141Q_or_out = A1L141Q_p1_out # !A1L78Q # phase0;
A1L141Q_reg_input = A1L141Q_or_out;
A1L141Q = DFFE(A1L141Q_reg_input, GLOBAL(clk), , rst, );


--readData_reg[3] is readData_reg[3]
readData_reg[3]_p0_out = !readData_reg[2] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[3];
readData_reg[3]_p1_out = readData_reg[2] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[3];
readData_reg[3]_p2_out = !readData_reg[2] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[3] & A1L86Q;
readData_reg[3]_p3_out = !readData_reg[2] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[3] & A1L76Q;
readData_reg[3]_p4_out = !readData_reg[2] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[3] & !A1L86Q & !A1L76Q;
readData_reg[3]_or_out = A1L501 # readData_reg[3]_p0_out # readData_reg[3]_p1_out # readData_reg[3]_p2_out # readData_reg[3]_p3_out # readData_reg[3]_p4_out;
readData_reg[3]_reg_input = readData_reg[3]_or_out;
readData_reg[3] = TFFE(readData_reg[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[4] is readData_reg[4]
readData_reg[4]_p0_out = !readData_reg[3] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[4];
readData_reg[4]_p1_out = readData_reg[3] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[4];
readData_reg[4]_p2_out = !readData_reg[3] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[4] & A1L86Q;
readData_reg[4]_p3_out = !readData_reg[3] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[4] & A1L76Q;
readData_reg[4]_p4_out = !readData_reg[3] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[4] & !A1L86Q & !A1L76Q;
readData_reg[4]_or_out = A1L701 # readData_reg[4]_p0_out # readData_reg[4]_p1_out # readData_reg[4]_p2_out # readData_reg[4]_p3_out # readData_reg[4]_p4_out;
readData_reg[4]_reg_input = readData_reg[4]_or_out;
readData_reg[4] = TFFE(readData_reg[4]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[5] is readData_reg[5]
readData_reg[5]_p0_out = !readData_reg[4] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[5];
readData_reg[5]_p1_out = readData_reg[4] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[5];
readData_reg[5]_p2_out = !readData_reg[4] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[5] & A1L86Q;
readData_reg[5]_p3_out = !readData_reg[4] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[5] & A1L76Q;
readData_reg[5]_p4_out = !readData_reg[4] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[5] & !A1L86Q & !A1L76Q;
readData_reg[5]_or_out = A1L901 # readData_reg[5]_p0_out # readData_reg[5]_p1_out # readData_reg[5]_p2_out # readData_reg[5]_p3_out # readData_reg[5]_p4_out;
readData_reg[5]_reg_input = readData_reg[5]_or_out;
readData_reg[5] = TFFE(readData_reg[5]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[6] is readData_reg[6]
readData_reg[6]_p0_out = !readData_reg[5] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[6];
readData_reg[6]_p1_out = readData_reg[5] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[6];
readData_reg[6]_p2_out = !readData_reg[5] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[6] & A1L86Q;
readData_reg[6]_p3_out = !readData_reg[5] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[6] & A1L76Q;
readData_reg[6]_p4_out = !readData_reg[5] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[6] & !A1L86Q & !A1L76Q;
readData_reg[6]_or_out = A1L111 # readData_reg[6]_p0_out # readData_reg[6]_p1_out # readData_reg[6]_p2_out # readData_reg[6]_p3_out # readData_reg[6]_p4_out;
readData_reg[6]_reg_input = readData_reg[6]_or_out;
readData_reg[6] = TFFE(readData_reg[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[7] is readData_reg[7]
readData_reg[7]_p0_out = !readData_reg[6] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & readData_reg[7];
readData_reg[7]_p1_out = readData_reg[6] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & A1L96Q & !readData_reg[7];
readData_reg[7]_p2_out = !readData_reg[6] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[7] & A1L86Q;
readData_reg[7]_p3_out = !readData_reg[6] & phase1 & A1L68Q & A1L36Q & A1L46Q & !A1L66Q & readData_reg[7] & A1L76Q;
readData_reg[7]_p4_out = !readData_reg[6] & phase1 & A1L68Q & A1L36Q & A1L46Q & A1L66Q & readData_reg[7] & !A1L86Q & !A1L76Q;
readData_reg[7]_or_out = A1L311 # readData_reg[7]_p0_out # readData_reg[7]_p1_out # readData_reg[7]_p2_out # readData_reg[7]_p3_out # readData_reg[7]_p4_out;
readData_reg[7]_reg_input = readData_reg[7]_or_out;
readData_reg[7] = TFFE(readData_reg[7]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L511 is reduce_or~2464
A1L511_p0_out = A1L06Q & readData_reg[7];
A1L511_p1_out = A1L26Q & writeData_reg[1] & !writeData_reg[3] & !writeData_reg[2] & !writeData_reg[0];
A1L511_p2_out = !A1L26Q & readData_reg[2] & !readData_reg[1] & readData_reg[3] & !readData_reg[0];
A1L511_p3_out = readData_reg[2] & readData_reg[1] & !readData_reg[3] & readData_reg[0] & A1L06Q;
A1L511_p4_out = !A1L26Q & !A1L06Q;
A1L511_or_out = A1L331 # A1L511_p0_out # A1L511_p1_out # A1L511_p2_out # A1L511_p3_out # A1L511_p4_out;
A1L511 = A1L511_or_out;


--A1L611 is reduce_or~2465
A1L611 = EXP(readData_reg[1] & !readData_reg[2]);


--A1L711 is reduce_or~2466
A1L711 = EXP(!readData_reg[1] & readData_reg[2]);


--A1L811 is reduce_or~2467
A1L811 = EXP(!writeData_reg[2] & !writeData_reg[1]);


--A1L911 is reduce_or~2468
A1L911 = EXP(writeData_reg[2] & writeData_reg[1]);


--A1L021 is reduce_or~2469
A1L021 = EXP(!readData_reg[1] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & readData_reg[2] & A1L06Q & !readData_reg[3]);


--A1L121 is reduce_or~2470
A1L121 = EXP(!A1L06Q & !A1L26Q);


--A1L221 is reduce_or~2471
A1L221 = EXP(A1L06Q & A1L26Q);


--A1L321 is reduce_or~2472
A1L321 = EXP(!writeData_reg[2] & !writeData_reg[3] & !writeData_reg[1] & !A1L06Q);


--A1L421 is reduce_or~2477
A1L421_p1_out = A1L021 & A1L121 & A1L221 & A1L321;
A1L421_p0_out = A1L021 & A1L121 & A1L221 & A1L321 & !A1L06Q & A1L911 & writeData_reg[0];
A1L421_p2_out = A1L021 & A1L121 & A1L221 & A1L321 & A1L611 & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & !readData_reg[0] & A1L06Q;
A1L421_p3_out = A1L021 & A1L121 & A1L221 & A1L321 & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & A1L06Q & A1L711 & readData_reg[3];
A1L421_p4_out = A1L021 & A1L121 & A1L221 & A1L321 & !A1L06Q & A1L811 & writeData_reg[3];
A1L421_or_out = A1L421_p0_out # A1L421_p2_out # A1L421_p3_out # A1L421_p4_out;
A1L421 = A1L421_p1_out $ A1L421_or_out;


--A1L521 is reduce_or~2480
A1L521 = EXP(!readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7]);


--A1L621 is reduce_or~2481
A1L621 = EXP(readData_reg[0] & !readData_reg[1]);


--A1L721 is reduce_or~2482
A1L721 = EXP(!writeData_reg[0] & !writeData_reg[1]);


--A1L821 is reduce_or~2488
A1L821_p0_out = !A1L06Q & A1L26Q & writeData_reg[3] & !writeData_reg[2] & A1L721;
A1L821_p1_out = !readData_reg[3] & readData_reg[1] & !readData_reg[0] & !readData_reg[2] & A1L06Q & !A1L26Q;
A1L821_p2_out = !A1L06Q & A1L26Q & !writeData_reg[3] & writeData_reg[1] & writeData_reg[0] & writeData_reg[2];
A1L821_p3_out = A1L06Q & !A1L26Q & A1L521;
A1L821_p4_out = readData_reg[3] & readData_reg[2] & A1L06Q & !A1L26Q & A1L621;
A1L821_or_out = A1L821_p0_out # A1L821_p1_out # A1L821_p2_out # A1L821_p3_out # A1L821_p4_out;
A1L821 = A1L821_or_out;


--A1L921 is reduce_or~2489
A1L921_p1_out = A1L06Q & !A1L26Q;
A1L921_p0_out = !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & !readData_reg[0] & A1L06Q & !A1L26Q & !readData_reg[2];
A1L921_p2_out = !readData_reg[1] & readData_reg[3] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & readData_reg[0] & A1L06Q & !A1L26Q;
A1L921_p3_out = readData_reg[1] & !readData_reg[3] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & readData_reg[0] & A1L06Q & !A1L26Q;
A1L921_p4_out = !readData_reg[1] & !readData_reg[3] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & !readData_reg[0] & A1L06Q & !A1L26Q;
A1L921_or_out = A1L431 # A1L921_p0_out # A1L921_p2_out # A1L921_p3_out # A1L921_p4_out;
A1L921 = A1L921_p1_out $ A1L921_or_out;


--A1L031 is reduce_or~2502
A1L031_p0_out = A1L06Q & !A1L26Q & A1L521;
A1L031_p1_out = readData_reg[3] & !readData_reg[2] & !readData_reg[0] & readData_reg[1] & A1L06Q & !A1L26Q;
A1L031_p2_out = !readData_reg[2] & readData_reg[0] & !readData_reg[1] & A1L06Q & !A1L26Q;
A1L031_p3_out = !A1L06Q & A1L26Q & writeData_reg[2] & writeData_reg[3] & writeData_reg[1] & writeData_reg[0];
A1L031_p4_out = !A1L06Q & A1L26Q & writeData_reg[2] & !writeData_reg[1] & !writeData_reg[0];
A1L031_or_out = A1L531 # A1L031_p0_out # A1L031_p1_out # A1L031_p2_out # A1L031_p3_out # A1L031_p4_out;
A1L031 = A1L031_or_out;


--A1L131 is reduce_or~2509
A1L131_p0_out = A1L06Q & !A1L26Q & A1L521;
A1L131_p1_out = readData_reg[0] & readData_reg[3] & !readData_reg[1] & readData_reg[2] & A1L06Q & !A1L26Q;
A1L131_p2_out = readData_reg[0] & readData_reg[3] & readData_reg[1] & !readData_reg[2] & A1L06Q & !A1L26Q;
A1L131_p3_out = !A1L06Q & A1L26Q & !writeData_reg[0] & writeData_reg[3] & !writeData_reg[1] & !writeData_reg[2];
A1L131_p4_out = !A1L06Q & A1L26Q & !writeData_reg[0] & writeData_reg[3] & writeData_reg[1] & writeData_reg[2];
A1L131_or_out = A1L631 # A1L131_p0_out # A1L131_p1_out # A1L131_p2_out # A1L131_p3_out # A1L131_p4_out;
A1L131 = A1L131_or_out;


--A1L231 is reduce_or~2515
A1L231_p0_out = !A1L06Q & A1L26Q & !writeData_reg[0] & !writeData_reg[3];
A1L231_p1_out = readData_reg[5] & A1L06Q & !A1L26Q;
A1L231_p2_out = A1L06Q & !A1L26Q & readData_reg[6];
A1L231_p3_out = A1L06Q & !A1L26Q & readData_reg[7];
A1L231_p4_out = A1L06Q & !A1L26Q & readData_reg[0] & !readData_reg[3];
A1L231_or_out = A1L731 # A1L231_p0_out # A1L231_p1_out # A1L231_p2_out # A1L231_p3_out # A1L231_p4_out;
A1L231 = A1L231_or_out;


--A1L11 is Select~6482
A1L11_p0_out = !A1L68Q & !A1L78Q;
A1L11_p1_out = A1L66Q & !A1L96Q & !A1L86Q & !A1L76Q & !A1L36Q & phase3 & !A1L56Q & !A1L68Q;
A1L11_p2_out = A1L66Q & !A1L96Q & !A1L86Q & !A1L76Q & phase3 & A1L68Q & !A1L46Q;
A1L11_p3_out = A1L66Q & !A1L96Q & !A1L86Q & !A1L76Q & phase3 & !A1L56Q & !A1L46Q;
A1L11_p4_out = A1L66Q & !A1L96Q & !A1L86Q & !A1L36Q & phase3 & A1L56Q & A1L68Q & !A1L46Q;
A1L11 = A1L11_p0_out # A1L11_p1_out # A1L11_p2_out # A1L11_p3_out # A1L11_p4_out;


--A1L21 is Select~6488
A1L21_p0_out = !A1L96Q & !A1L86Q & !link & A1L68Q & A1L46Q & A1L66Q & !A1L36Q;
A1L21_p1_out = !A1L96Q & !A1L86Q & !A1L76Q & !link & !phase1;
A1L21_p2_out = !A1L96Q & !A1L86Q & !A1L76Q & !link & !A1L68Q & A1L46Q;
A1L21_p3_out = !A1L96Q & !A1L76Q & !link & A1L66Q;
A1L21_p4_out = !A1L96Q & !A1L86Q & !link & phase1 & A1L46Q & A1L66Q & !A1L36Q;
A1L21 = A1L11 # A1L21_p0_out # A1L21_p1_out # A1L21_p2_out # A1L21_p3_out # A1L21_p4_out;


--A1L31 is Select~6494
A1L31_p0_out = A1L36Q & !link & !A1L56Q & A1L46Q & !A1L66Q;
A1L31_p1_out = !A1L96Q & !A1L86Q & !A1L76Q & A1L36Q & !A1L68Q & !link;
A1L31_p2_out = !A1L96Q & !A1L86Q & !A1L76Q & A1L36Q & !link & !A1L56Q;
A1L31_p3_out = A1L36Q & !A1L68Q & !link & A1L46Q;
A1L31_p4_out = !A1L76Q & A1L36Q & !link & !A1L56Q & A1L46Q;
A1L31 = A1L21 # A1L31_p0_out # A1L31_p1_out # A1L31_p2_out # A1L31_p3_out # A1L31_p4_out;


--A1L77 is inner_state~4153
A1L77_p0_out = A1L68Q & !A1L56Q & !A1L76Q & !A1L36Q & A1L46Q;
A1L77_p1_out = !A1L78Q & !A1L68Q;
A1L77_p2_out = !A1L68Q & A1L56Q & !A1L76Q & !A1L66Q;
A1L77_p3_out = !A1L68Q & A1L56Q & !A1L76Q & !A1L36Q & !A1L46Q;
A1L77_p4_out = !A1L68Q & !A1L76Q & A1L36Q & A1L46Q;
A1L77 = A1L77_p0_out # A1L77_p1_out # A1L77_p2_out # A1L77_p3_out # A1L77_p4_out;


--A1L87 is inner_state~4159
A1L87_p0_out = !A1L56Q & !A1L76Q & !A1L66Q & A1L07;
A1L87_p1_out = A1L36Q & !A1L86Q & !A1L96Q & !A1L56Q & phase3 & A1L68Q & A1L76Q & A1L66Q;
A1L87_p2_out = !A1L36Q & !A1L86Q & !A1L96Q & !A1L56Q & phase3 & !A1L68Q & A1L76Q & A1L66Q & A1L46Q & !phase1;
A1L87_p3_out = !A1L36Q & A1L86Q & A1L96Q & !A1L56Q & phase3 & !A1L68Q & !A1L66Q;
A1L87_p4_out = !A1L36Q & A1L86Q & A1L96Q & !A1L56Q & phase3 & !A1L68Q & A1L46Q & !phase1;
A1L87 = A1L77 # A1L87_p0_out # A1L87_p1_out # A1L87_p2_out # A1L87_p3_out # A1L87_p4_out;


--A1L97 is inner_state~4165
A1L97_p1_out = !A1L78Q & !A1L68Q;
A1L97 = A1L97_p1_out;


--A1L08 is inner_state~4167
A1L08_p0_out = !A1L96Q & !A1L76Q & A1L66Q;
A1L08_p1_out = !A1L68Q & !A1L46Q & !A1L96Q & A1L56Q & !A1L36Q;
A1L08_p2_out = !A1L68Q & A1L46Q & !A1L96Q & A1L36Q;
A1L08_p3_out = A1L68Q & A1L46Q & !A1L96Q & !A1L56Q & !A1L36Q;
A1L08_p4_out = !A1L96Q & !phase3;
A1L08 = A1L97 # A1L08_p0_out # A1L08_p1_out # A1L08_p2_out # A1L08_p3_out # A1L08_p4_out;


--A1L18 is inner_state~4173
A1L18_p1_out = A1L46Q & !A1L86Q & A1L36Q & !A1L68Q;
A1L18 = A1L18_p1_out;


--A1L28 is inner_state~4175
A1L28_p0_out = !A1L46Q & !A1L86Q & !A1L96Q & A1L66Q;
A1L28_p1_out = A1L46Q & !A1L86Q & !A1L36Q & A1L68Q & !A1L56Q;
A1L28_p2_out = !A1L46Q & !A1L86Q & !A1L36Q & !A1L68Q & A1L56Q;
A1L28_p3_out = !A1L86Q & !phase3;
A1L28_p4_out = !A1L86Q & !A1L96Q & !A1L76Q;
A1L28 = A1L18 # A1L28_p0_out # A1L28_p1_out # A1L28_p2_out # A1L28_p3_out # A1L28_p4_out;


--A1L38 is inner_state~4181
A1L38_p1_out = A1L36Q & A1L96Q & phase3 & !A1L76Q & A1L86Q & A1L68Q & !A1L66Q;
A1L38_p2_out = A1L96Q & phase3 & !A1L76Q & A1L86Q & A1L68Q & !A1L66Q & !A1L46Q;
A1L38_p3_out = A1L96Q & phase3 & !A1L76Q & A1L86Q & A1L68Q & !A1L66Q & A1L56Q;
A1L38_p4_out = !A1L36Q & A1L96Q & phase3 & !A1L76Q & A1L86Q & !A1L68Q & !A1L66Q & A1L46Q & A1L78Q;
A1L38 = A1L38_p1_out # A1L38_p2_out # A1L38_p3_out # A1L38_p4_out;


--A1L41 is Select~6500
A1L41_p1_out = !A1L76Q & A1L36Q & A1L46Q & sda_buf & !A1L66Q & !A1L86Q & !A1L96Q;
A1L41_p2_out = A1L36Q & A1L46Q & sda_buf & !phase0 & A1L96Q;
A1L41 = A1L41_p1_out # A1L41_p2_out;


--A1L51 is Select~6503
A1L51_p0_out = A1L36Q & A1L46Q & A1L66Q & sda_buf & A1L86Q;
A1L51_p1_out = A1L36Q & A1L46Q & !A1L66Q & sda_buf & !phase0;
A1L51_p2_out = !A1L76Q & A1L36Q & A1L46Q & sda_buf & !phase0;
A1L51_p3_out = A1L36Q & A1L46Q & A1L66Q & phase1 & A1L86Q;
A1L51_p4_out = !phase3 & A1L76Q & A1L36Q & A1L46Q & A1L66Q & sda_buf;
A1L51 = A1L41 # A1L51_p0_out # A1L51_p1_out # A1L51_p2_out # A1L51_p3_out # A1L51_p4_out;


--A1L61 is Select~6509
A1L61_p1_out = A1L56Q & phase3 & !A1L96Q & A1L76Q & A1L86Q;
A1L61 = A1L61_p1_out;


--A1L71 is Select~6511
A1L71_p0_out = A1L56Q & phase3 & !A1L86Q & !A1L66Q & !A1L76Q & !A1L96Q & link;
A1L71_p1_out = A1L56Q & sda_buf & !phase3 & A1L86Q;
A1L71_p2_out = A1L56Q & sda_buf & !A1L86Q & !A1L76Q & !A1L96Q & !phase1;
A1L71_p3_out = A1L56Q & sda_buf & A1L66Q & !A1L76Q;
A1L71_p4_out = A1L56Q & sda_buf & A1L86Q & A1L66Q;
A1L71 = A1L61 # A1L71_p0_out # A1L71_p1_out # A1L71_p2_out # A1L71_p3_out # A1L71_p4_out;


--A1L81 is Select~6517
A1L81_p0_out = A1L36Q & !A1L46Q & !phase3 & sda_buf & !A1L66Q;
A1L81_p1_out = A1L36Q & !A1L46Q & phase3 & !A1L66Q & !A1L96Q & !A1L76Q & A1L86Q;
A1L81_p2_out = A1L36Q & !A1L46Q & sda_buf & !A1L96Q & !A1L76Q;
A1L81_p3_out = A1L36Q & !A1L46Q & phase3 & A1L96Q & A1L76Q & A1L86Q;