Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.56 s | Elapsed : 0.00 / 1.00 s --> Reading design: left_right_leds.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "left_right_leds.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "left_right_leds"Output Format                      : NGCTarget Device                      : xc3s500e-4-fg320---- Source OptionsTop Module Name                    : left_right_ledsAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : left_right_leds.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "F:/xillinx/mywork/ledleft/left_right_leds.vhd" in Library work.Architecture behavioral of Entity left_right_leds is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <left_right_leds> (Architecture <behavioral>).INFO:Xst:1561 - "F:/xillinx/mywork/ledleft/left_right_leds.vhd" line 122: Mux is complete : default of case is discardedEntity <left_right_leds> analyzed. Unit <left_right_leds> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <left_right_leds>.    Related source file is "F:/xillinx/mywork/ledleft/left_right_leds.vhd".    Found 8-bit register for signal <led>.    Found 1-bit 4-to-1 multiplexer for signal <$n0006> created at line 110.    Found 1-bit 4-to-1 multiplexer for signal <$n0007> created at line 110.    Found 1-bit register for signal <delay_rotary_q1>.    Found 8-bit register for signal <led_drive>.    Found 8-bit register for signal <led_pattern>.    Found 1-bit register for signal <rotary_a_in>.    Found 1-bit register for signal <rotary_b_in>.    Found 1-bit register for signal <rotary_event>.    Found 2-bit register for signal <rotary_in>.    Found 1-bit register for signal <rotary_left>.    Found 1-bit register for signal <rotary_press_in>.    Found 1-bit register for signal <rotary_q1>.    Found 1-bit register for signal <rotary_q2>.    Summary:	inferred  34 D-type flip-flop(s).	inferred   2 Multiplexer(s).Unit <left_right_leds> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 12 1-bit register                    : 8 2-bit register                    : 1 8-bit register                    : 3# Multiplexers                     : 2 1-bit 4-to-1 multiplexer          : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <left_right_leds> ...Loading device for application Rf_Device from file '3s500e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block left_right_leds, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : left_right_leds.ngrTop Level Output File Name         : left_right_ledsOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 12Macro Statistics :# Registers                        : 12#      1-bit register              : 8#      2-bit register              : 1#      8-bit register              : 3# Multiplexers                     : 2#      1-bit 4-to-1 multiplexer    : 2Cell Usage :# BELS                             : 21#      LUT2                        : 2#      LUT2_L                      : 8#      LUT3_L                      : 10#      VCC                         : 1# FlipFlops/Latches                : 34#      FD                          : 24#      FDE                         : 9#      FDR                         : 1# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 11#      IBUF                        : 3#      OBUF                        : 8=========================================================================Device utilization summary:---------------------------Selected Device : 3s500efg320-4  Number of Slices:                      20  out of   4656     0%   Number of Slice Flip Flops:            34  out of   9312     0%   Number of 4 input LUTs:                20  out of   9312     0%   Number of bonded IOBs:                 12  out of    232     5%   Number of GCLKs:                        1  out of     24     4%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 34    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 4.102ns (Maximum Frequency: 243.784MHz)   Minimum input arrival time before clock: 2.447ns   Maximum output required time after clock: 7.986ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'  Clock period: 4.102ns (frequency: 243.784MHz)  Total number of paths / destination ports: 70 / 40-------------------------------------------------------------------------Delay:               4.102ns (Levels of Logic = 1)  Source:            rotary_q1 (FF)  Destination:       rotary_event (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: rotary_q1 to rotary_event                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               4   0.455   1.122  rotary_q1 (rotary_q1)     LUT2:I0->O            1   0.757   0.801  _n00101 (_n0010)     FDR:R                     0.967          rotary_event    ----------------------------------------    Total                      4.102ns (2.179ns logic, 1.923ns route)                                       (53.1% logic, 46.9% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'  Total number of paths / destination ports: 3 / 3-------------------------------------------------------------------------Offset:              2.447ns (Levels of Logic = 1)  Source:            rotary_b (PAD)  Destination:       rotary_b_in (FF)  Destination Clock: clk rising  Data Path: rotary_b to rotary_b_in                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             1   1.228   0.801  rotary_b_IBUF (rotary_b_IBUF)     FD:D                      0.418          rotary_b_in    ----------------------------------------    Total                      2.447ns (1.646ns logic, 0.801ns route)                                       (67.3% logic, 32.7% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'  Total number of paths / destination ports: 8 / 8-------------------------------------------------------------------------Offset:              7.986ns (Levels of Logic = 1)  Source:            led_7 (FF)  Destination:       led<7> (PAD)  Source Clock:      clk rising  Data Path: led_7 to led<7>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               1   0.455   0.801  led_7 (led_7)     OBUF:I->O                 6.730          led_7_OBUF (led<7>)    ----------------------------------------    Total                      7.986ns (7.185ns logic, 0.801ns route)                                       (90.0% logic, 10.0% route)=========================================================================CPU : 6.38 / 7.03 s | Elapsed : 6.00 / 7.00 s --> Total memory usage is 114824 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    1 (   0 filtered)