library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fenpinqi89 is
 port(clk :in std_logic;
      control:in std_logic;
      output:out std_logic;
      count_ctrl:out std_logic);
end fenpinqi89;

architecture main of fenpinqi89 is
signal counter00,counter01:std_logic;
signal counter1:integer range 0 to 7;
signal counter2:integer range 0 to 8;
signal cp1,cp2,p,q:std_logic;
begin

process(clk,control)
begin
if falling_edge(clk) then
   if control='0' then 
        if counter1=7 then counter1<=0; counter00<='1';
             else counter1<=counter1+1;counter00<='0';
        end if;
        if(counter1<=3) then cp1<='0';
             else cp1<='1';
        end if;
    end if;
 end if;
p<=counter00;
end process;

process(clk,control)
begin
   if falling_edge(clk) then
     if control='1' then 
        if counter2=8 then counter2<=0; counter01<='1';
             else counter2<=counter2+1;counter01<='0';
        end if;
        if(counter2<=3) then cp2<='0';
             else cp2<='1';
        end if;
     end if;
 end if;
q<=counter01;
end process;
count_ctrl<=p or q;

process(clk,control)
begin
if falling_edge(clk) then
   if control='0' then output<=cp1;
      else output<=cp2;
   end if;
end if;
end process;

end main;