library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity leijiaqi is
port(clk:in std_logic;
       y:out std_logic);
end;

architecture main of leijiaqi is

signal count : std_logic_vector(29 downto 0):="000000000000000000000000000000";
constant step : integer := 127918701;
begin

p1: process(clk)
begin
if rising_edge(clk) then
	count<=count+step;
end if;
end process;
y<=count(29);

end;