?? full_function.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity full_function is
port( na_clk : in std_logic;
na_y : out std_logic;
na_output : out std_logic);
end;
architecture main of full_function is
component fenpinqi89
port(clk: in std_logic;
control:in std_logic;
output: out std_logic;
count_ctrl: out std_logic);
end component;
component controller
port(clk:in std_logic;
count_ctrl: in std_logic;
control_signal:out std_logic);
end component;
component leijiaqi
port(clk:in std_logic;
y:out std_logic);
end component;
signal temp1,temp2:std_logic;
begin
a1:fenpinqi89 port map(na_clk,temp1,na_output,temp2);
a2:controller port map(na_clk,temp2,temp1);
a3:leijiaqi port map(na_clk,na_y);
end main;
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