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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file multi_16x16.v when simulating
// the core, multi_16x16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module multi_16x16(
	clk,
	a,
	b,
	q,
	aclr);


input clk;
input [15 : 0] a;
input [15 : 0] b;
output [31 : 0] q;
input aclr;

// synopsys translate_off

      MULT_GEN_V7_0 #(
		9,	// bram_addr_width
		0,	// c_a_type
		16,	// c_a_width
		16,	// c_baat
		0,	// c_b_constant
		0,	// c_b_type
		"0000000000000001",	// c_b_value
		16,	// c_b_width
		1,	// c_enable_rlocs
		1,	// c_has_aclr
		0,	// c_has_a_signed
		1,	// c_has_b
		0,	// c_has_ce
		0,	// c_has_loadb
		0,	// c_has_load_done
		0,	// c_has_nd
		0,	// c_has_o
		1,	// c_has_q
		0,	// c_has_rdy
		0,	// c_has_rfd
		0,	// c_has_sclr
		0,	// c_has_swapb
		"mem",	// c_mem_init_prefix
		0,	// c_mem_type
		0,	// c_mult_type
		0,	// c_output_hold
		32,	// c_out_width
		0,	// c_pipeline
		1,	// c_reg_a_b_inputs
		0,	// c_sqm_type
		1,	// c_stack_adders
		1,	// c_standalone
		1,	// c_sync_enable
		1,	// c_use_luts
		0)	// c_v2_speed
	inst (
		.CLK(clk),
		.A(a),
		.B(b),
		.Q(q),
		.ACLR(aclr),
		.O(),
		.A_SIGNED(),
		.LOADB(),
		.LOAD_DONE(),
		.SWAPB(),
		.CE(),
		.SCLR(),
		.RFD(),
		.ND(),
		.RDY());


// synopsys translate_on

endmodule