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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
multi_16x16 YourInstanceName (
	.clk(clk),
	.a(a),
	.b(b),
	.q(q),
	.aclr(aclr));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file multi_16x16.v when simulating
// the core, multi_16x16. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".