`timescale 1ns/1psmodule mux4(mux4_out,m0_in,m1_in,m2_in,m3_in,sel_in);    parameter width=8;        output[width-1:0] mux4_out;    input[width-1:0] m0_in;    input[width-1:0] m1_in;    input[width-1:0] m2_in;    input[width-1:0] m3_in;    input[1:0] sel_in;        reg [width-1:0] mux4_out;        always @(m0_in or m1_in or m2_in or m3_in or sel_in)    begin        case(sel_in)            'b00:mux4_out=m0_in;            'b01:mux4_out=m1_in;            'b10:mux4_out=m2_in;            'b11:mux4_out=m3_in;        endcase    endendmodule