?? memory.v
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/*`timescale 1ns/1psmodule memory(mem_out,mem_in,mem_address,RW); parameter width=8; output[width-1:0] mem_out; input [width-1:0] mem_in; input [width-1:0] mem_address; input RW; reg [width-1:0] mem_out; reg [width-1:0] mem[255:0]; always @(mem_in or mem_address or RW) begin if(!RW) mem_out=mem[mem_address]; else mem[mem_address]=mem_in; endendmodule*/`timescale 1ns/1psmodule memory(mem_data,mem_address,CS,WRITE,READ); parameter width=8; inout [width-1:0] mem_data; //?????? input [7:0] mem_address; //?????? input CS,WRITE,READ; //???? wire [width-1:0] mem_in; // reg [width-1:0] mem_out; //???? reg [width-1:0] mem[255:0]; //256?? 快捷鍵說明
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