`timescale 1ns/1psmodule mux8(mux8_out,m0_in,m1_in,m2_in,m3_in,m4_in,m5_in,m6_in,m7_in,sel_in);    parameter width=8;        output[width-1:0] mux8_out;    input[width-1:0] m0_in;    input[width-1:0] m1_in;    input[width-1:0] m2_in;    input[width-1:0] m3_in;    input[width-1:0] m4_in;    input[width-1:0] m5_in;    input[width-1:0] m6_in;    input[width-1:0] m7_in;    input[2:0] sel_in;        reg [width-1:0] mux8_out;        always @(m0_in or m1_in or m2_in or m3_in or m4_in or m5_in or m6_in or m7_in or sel_in)    begin        case(sel_in)            'b00:mux8_out=m0_in;            'b01:mux8_out=m1_in;            'b10:mux8_out=m2_in;            'b011:mux8_out=m3_in;            'b100:mux8_out=m4_in;            'b101:mux8_out=m5_in;            'b110:mux8_out=m6_in;            'b111:mux8_out=m7_in;        endcase    endendmodule