`timescale 1ns/1psmodule PC(pc_out,pc_in,clk,reset,load_enable,count_enable);    parameter width=8;        output[width-1:0] pc_out;    input[width-1:0] pc_in;    input clk;    input reset;    input load_enable;    input count_enable;    reg [width-1:0] pc_out;        always @(posedge clk or negedge reset)    begin        if(!reset)        pc_out<='b0;        else        if(load_enable)        pc_out<=pc_in;        else        if(count_enable)        pc_out<=pc_out+1;        else        pc_out<=pc_out;    end    endmodule