`timescale 1ns/1nsmodule testbench;reg clk;reg rst;reg codein;wire [1:0] codeoutv;wire [1:0] codeoutb;initial  begin    clk<=0;    rst<=0;    codein<=0;    #20 codein<=1;    #5  rst<=1;    #15 codein<=0;    codein_ge1;    codein_ge2;    codein_ge1;    codein_ge2;    codein_ge1;    codein_ge2;    codein_ge1;    codein_ge2;    codein_ge1;    codein_ge2;      endtask codein_ge1;  begin    #20 codein<=1;    #40 codein<=0;    #40 codein<=1;    #20 codein<=0;    #100 codein<=1;    #20 codein<=0;  endendtasktask codein_ge2;  begin    #20 codein<=1;    #40 codein<=0;    #20 codein<=1;    #40 codein<=0;    #100 codein<=1;    #20 codein<=0;  endendtaskalways #10 clk=~clk;decode inst0(	.clk(clk),	.rst(rst),	.codein(codein),	.codeoutv(codeoutv),	.codeoutb(codeoutb)	);/*	insert_b inb(   .clk(clk),   .rst(rst),   .codeinv(codeoutv),   .codeoutb(codeoutb)   );*/endmodule