library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sub4 is
port( A: in std_logic_vector(3 downto 0);
      B: in std_logic_vector(3 downto 0);
      D: out std_logic_vector(3 downto 0));
end sub4;
architecture rt of sub4 is
signal aa,bb,ss: std_logic_vector(4 downto 0);
signal v:std_logic;
begin 
      aa<='0' & A;
      bb<='0' & not B;
      SS<=aa + bb + '1';
      v<=ss(4);
      D(3 downto 0)<= ss(3 downto 0);
end rt;