?? spi_prog.vhd
字號:
INIT_17 => X"557D2201011FE004C008E002011202C7E004C008E002010E012AA000556F2201",
INIT_18 => X"6004A00001121270011212800112129001120202E004C008E002010E012AA000",
INIT_19 => X"A000559CC10101970128A0005598C001000BA00055932201011FE004C008E002",
INIT_1A => X"C000A00055ABC40101A50414A00055A6C30101A00314A00055A1C201019B0219",
INIT_1B => X"51B04F114F0141B955BD20084000A000C00151B94F134F0141B055B420084000",
INIT_1C => X"B8004061A000803AC1015DC8C00A81010130A000CF1041C151C52001400041B9",
INIT_1D => X"02069200020602061200B80001D47010A000C0F6B80080C6A000A0DFBC00407B",
INIT_1E => X"01F2A00F1010120001F2000E000E000E000E1100A0009200B80001D470108101",
INIT_1F => X"108001F71090A00001C11F1001C11F2001E6A000803A800759F5C00AA0001100",
INIT_20 => X"D030B8000211102003060306030603061300B80002111030A00001F7107001F7",
INIT_21 => X"A00001C10F0DA000800AA000C0F6B80080075E1BC011B800C0E9B80080B9A000",
INIT_22 => X"0F6C01C10F4201C10F6F01C10F6301C10F6901C10F50021D021DA00001C10F20",
INIT_23 => X"0F46022001C10F4901C10F5001C10F53022001C10F6501C10F7A01C10F6101C1",
INIT_24 => X"01C10F6F01C10F7201C10F50022001C10F4801C10F5301C10F4101C10F4C01C1",
INIT_25 => X"0F76022001C10F7201C10F6501C10F6D01C10F6D01C10F6101C10F7201C10F67",
INIT_26 => X"01C10F6101C10F57A000021D021D01C10F3001C10F3001C10F2E01C10F3101C1",
INIT_27 => X"0F7201C10F6F01C10F66022001C10F6701C10F6E01C10F6901C10F7401C10F69",
INIT_28 => X"0F6501C10F6C01C10F6901C10F46022001C10F5301C10F4301C10F4D022001C1",
INIT_29 => X"0F6701C10F6F01C10F7201C10F50022001C10F6E01C10F6902AAA000021D01C1",
INIT_2A => X"01C10F6101C10F7201C10F45A000021D01C101C10F7301C10F6501C10F7201C1",
INIT_2B => X"01C10F45021DA000021D01C10F4B01C10F4F021DA000022001C10F6501C10F73",
INIT_2C => X"0F6501C10F5301C10F2D01C10F53021D01C101C10F6C01C10F6102AA01C10F2D",
INIT_2D => X"01C10F2D01C10F50021D02AA022001C10F7201C10F6F01C10F7401C10F6301C1",
INIT_2E => X"0F52028101C10F6D01C10F6101C10F7201C10F6701C10F6F01C10F7201C10F50",
INIT_2F => X"01C10F49021D031F022001C10F6401C10F6101C10F6501C10F5201C10F2D01C1",
INIT_30 => X"0328022001C10F6501C10F6301C10F6901C10F7601C10F6501C10F4401C10F2D",
INIT_31 => X"0F70A000021D01C10F7001C10F6C01C10F6501C10F4801C10F2D01C10F48021D",
INIT_32 => X"01C10F43021DA00001C10F4401C10F49A00001C10F6501C10F6701C10F6101C1",
INIT_33 => X"01C10F2802AA022001C10F6D01C10F7201C10F6901C10F6601C10F6E01C10F6F",
INIT_34 => X"0F6F01C10F6201C10F41021DA000022001C10F2901C10F6E01C10F2F01C10F59",
INIT_35 => X"0F7201C101C10F6401C10F610220031F021DA000021D01C10F7401C10F7201C1",
INIT_36 => X"0000000000000000000000000000A00001C10F3D01C101C10F7301C10F6501C1",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"43F580016000C010001143FC001353FB20104000E00000000000000000000000",
INITP_00 => X"D351DFDF2CCFFCF3CDFFFFFCCCCCFDFFFFFF7FFFCF3CF3FB3FFCF777777CFFFF",
INITP_01 => X"3DDC0302CF7700F7302F7715F3F2118674436CC99F72E7F7AB53D57DA03D3D34",
INITP_02 => X"DE8CA3EDE8CCCCA3EA3CCCCA3A8333CA3A8CA3A8CA3A8F28ED88920A8B3DDD3B",
INITP_03 => X"32CCE5D8C0EA89B19A2C998999752BD3D3D2F4F4EDCB72DCB72D2DE82CCCCA3E",
INITP_04 => X"333CCCCCCCBF33333CCCCCCCCCCF33333CCCF333333333ECB26676662CAA2CB3",
INITP_05 => X"CFF333333CCCCCCCCCFF33333333F33CCEF33BCCCCCBF3333333CCEF3333CCCF",
INITP_06 => X"000000000002CF333CCFEF33333BCCCCCFCCCCCCCECCB3332F333333FCCCCCCC",
INITP_07 => X"F233480000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DIB => "0000000000000000",
DIPB => "00",
ENB => '1',
WEB => '0',
SSRB => '0',
CLKB => clk,
ADDRB => address,
DOB => instruction(15 downto 0),
DOPB => instruction(17 downto 16),
DIA => jdata,
DIPA => jparity,
ENA => sel1,
WEA => '1',
SSRA => '0',
CLKA => update,
ADDRA=> jaddr,
DOA => doa(7 downto 0),
DOPA => dopa);
v2_bscan: BSCAN_VIRTEX2
port map( TDO1 => tdo1,
TDO2 => tdo2,
UPDATE => update,
SHIFT => shift,
RESET => reset,
TDI => tdi,
SEL1 => sel1,
DRCK1 => drck1,
SEL2 => sel2,
DRCK2 => drck2,
CAPTURE => capture);
--buffer signal used as a clock
upload_clock: BUFG
port map( I => drck1,
O => drck1_buf);
-- Assign the reset to be active whenever the uploading subsystem is active
proc_reset <= sel1;
srlC1: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tdi,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(10),
Q15 => jaddr(8));
flop1: FD
port map ( D => jaddr(10),
Q => jaddr(9),
C => drck1_buf);
srlC2: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(8),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(7),
Q15 => tap5);
flop2: FD
port map ( D => jaddr(7),
Q => jaddr(6),
C => drck1_buf);
srlC3: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap5,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(5),
Q15 => jaddr(3));
flop3: FD
port map ( D => jaddr(5),
Q => jaddr(4),
C => drck1_buf);
srlC4: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jaddr(3),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(2),
Q15 => tap11);
flop4: FD
port map ( D => jaddr(2),
Q => jaddr(1),
C => drck1_buf);
srlC5: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap11,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jaddr(0),
Q15 => jdata(7));
flop5: FD
port map ( D => jaddr(0),
Q => jparity(0),
C => drck1_buf);
srlC6: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(7),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(6),
Q15 => tap17);
flop6: FD
port map ( D => jdata(6),
Q => jdata(5),
C => drck1_buf);
srlC7: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => tap17,
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(4),
Q15 => jdata(2));
flop7: FD
port map ( D => jdata(4),
Q => jdata(3),
C => drck1_buf);
srlC8: SRLC16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => jdata(2),
CE => '1',
CLK => drck1_buf,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => jdata(1),
Q15 => tdo1);
flop8: FD
port map ( D => jdata(1),
Q => jdata(0),
C => drck1_buf);
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE spi_prog.vhd
--
------------------------------------------------------------------------------------
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