.O(int_enable_value ))/* synthesis xc_props = "INIT=04"*/;

 FDRE int_enable_flop ( 
 .D(int_enable_value),
 .Q(int_enable),
 .CE(int_update_enable),
 .R(internal_reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// Decodes for the control of the program counter and CALL/RETURN stack
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam move_group_lut.INIT = 16'h7400 ;
 // synthesis translate_on 
 LUT4 move_group_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(move_group))/* synthesis xc_props = "INIT=7400"*/;

 // synthesis translate_off 
 defparam condition_met_lut.INIT = 16'h5A3C ;
 // synthesis translate_on 
 LUT4 condition_met_lut ( 
 .I0(carry_flag),
 .I1(zero_flag),
 .I2(instruction[10]),
 .I3(instruction[11]),
 .O(condition_met))/* synthesis xc_props = "INIT=5A3C"*/;

 // synthesis translate_off 
 defparam normal_count_lut.INIT = 8'h2F ;
 // synthesis translate_on 
 LUT3 normal_count_lut ( 
 .I0(instruction[12]),
 .I1(condition_met),
 .I2(move_group),
 .O(normal_count ))/* synthesis xc_props = "INIT=2F"*/;

 // synthesis translate_off 
 defparam call_type_lut.INIT = 16'h1000;
 // synthesis translate_on 
 LUT4 call_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(call_type ))/* synthesis xc_props = "INIT=1000"*/;

 // synthesis translate_off 
 defparam push_pop_lut.INIT = 16'h5400;
 // synthesis translate_on 
 LUT4 push_pop_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(push_or_pop_type))/* synthesis xc_props = "INIT=5400"*/;

 // synthesis translate_off 
 defparam valid_move_lut.INIT = 4'hD;
 // synthesis translate_on 
 LUT2 valid_move_lut ( 
 .I0(instruction[12]),
 .I1(condition_met),
 .O(valid_to_move ))/* synthesis xc_props = "INIT=D"*/;
//
////////////////////////////////////////////////////////////////////////////////////
//
// The ZERO and CARRY Flags
//
////////////////////////////////////////////////////////////////////////////////////
//
 // Enable for flags

 // synthesis translate_off 
 defparam flag_type_lut.INIT = 16'h41FC;
 // synthesis translate_on 
 LUT4 flag_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(flag_type ))/* synthesis xc_props = "INIT=41FC"*/;

 FD flag_write_flop ( 
 .D(flag_type),
 .Q(flag_write),
 .C(clk));

 // synthesis translate_off 
 defparam flag_enable_lut.INIT = 4'h8;
 // synthesis translate_on 
 LUT2 flag_enable_lut ( 
 .I0(t_state),
 .I1(flag_write),
 .O(flag_enable))/* synthesis xc_props = "INIT=8"*/;

 // Zero Flag

 // synthesis translate_off 
 defparam low_zero_lut.INIT = 16'h0001;
 // synthesis translate_on 
 LUT4 low_zero_lut ( 
 .I0(alu_result[0]),
 .I1(alu_result[1]),
 .I2(alu_result[2]),
 .I3(alu_result[3]),
 .O(low_zero ))/* synthesis xc_props = "INIT=0001"*/;

 // synthesis translate_off 
 defparam high_zero_lut.INIT = 16'h0001;
 // synthesis translate_on 
 LUT4 high_zero_lut ( 
 .I0(alu_result[4]),
 .I1(alu_result[5]),
 .I2(alu_result[6]),
 .I3(alu_result[7]),
 .O(high_zero ))/* synthesis xc_props = "INIT=0001"*/;

 MUXCY low_zero_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(low_zero),
 .O(low_zero_carry));

 MUXCY high_zero_cymux ( 
 .DI(1'b0),
 .CI(low_zero_carry),
 .S(high_zero),
 .O(high_zero_carry));

 // synthesis translate_off 
 defparam sel_shadow_zero_lut.INIT = 8'h3F;
 // synthesis translate_on 
 LUT3 sel_shadow_zero_lut ( 
 .I0(shadow_zero),
 .I1(instruction[16]),
 .I2(instruction[17]),
 .O(sel_shadow_zero ))/* synthesis xc_props = "INIT=3F"*/;

 MUXCY zero_cymux ( 
 .DI(shadow_zero),
 .CI(high_zero_carry),
 .S(sel_shadow_zero),
 .O(zero_carry ));

 XORCY zero_xor( 
 .LI(1'b0),
 .CI(zero_carry),
 .O(zero_fast_route));
             
 FDRE zero_flag_flop ( 
 .D(zero_fast_route),
 .Q(zero_flag),
 .CE(flag_enable),
 .R(internal_reset),
 .C(clk));

 // Parity detection

 // synthesis translate_off 
 defparam low_parity_lut.INIT = 16'h6996;
 // synthesis translate_on 
 LUT4 low_parity_lut ( 
 .I0(logical_result[0]),
 .I1(logical_result[1]),
 .I2(logical_result[2]),
 .I3(logical_result[3]),
 .O(low_parity ))/* synthesis xc_props = "INIT=6996"*/;

 // synthesis translate_off 
 defparam high_parity_lut.INIT = 16'h6996;
 // synthesis translate_on 
 LUT4 high_parity_lut ( 
 .I0(logical_result[4]),
 .I1(logical_result[5]),
 .I2(logical_result[6]),
 .I3(logical_result[7]),
 .O(high_parity ))/* synthesis xc_props = "INIT=6996"*/;

 MUXCY parity_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(low_parity),
 .O(parity_carry) );

 XORCY parity_xor ( 
 .LI(high_parity),
 .CI(parity_carry),
 .O(parity));

 // CARRY flag selection

 // synthesis translate_off 
 defparam sel_parity_lut.INIT = 16'hF3FF;
 // synthesis translate_on 
 LUT4 sel_parity_lut ( 
 .I0(parity),
 .I1(instruction[13]),
 .I2(instruction[15]),
 .I3(instruction[16]),
 .O(sel_parity ))/* synthesis xc_props = "INIT=F3FF"*/;

 // synthesis translate_off 
 defparam sel_arith_carry_lut.INIT = 8'hF3;
 // synthesis translate_on 
 LUT3 sel_arith_carry_lut ( 
 .I0(arith_carry),
 .I1(instruction[16]),
 .I2(instruction[17]),
 .O(sel_arith_carry ))/* synthesis xc_props = "INIT=F3"*/;

 // synthesis translate_off 
 defparam sel_shift_carry_lut.INIT = 4'hC;
 // synthesis translate_on 
 LUT2 sel_shift_carry_lut ( 
 .I0(shift_carry),
 .I1(instruction[15]),
 .O(sel_shift_carry ))/* synthesis xc_props = "INIT=C"*/;

 // synthesis translate_off 
 defparam sel_shadow_carry_lut.INIT = 4'h3;
 // synthesis translate_on 
 LUT2 sel_shadow_carry_lut ( 
 .I0(shadow_carry),
 .I1(instruction[17]),
 .O(sel_shadow_carry ))/* synthesis xc_props = "INIT=3"*/;

 MUXCY sel_shadow_muxcy ( 
 .DI(shadow_carry),
 .CI(1'b0),
 .S(sel_shadow_carry),
 .O(sel_carry[0]) );

 MUXCY sel_shift_muxcy ( 
 .DI(shift_carry),
 .CI(sel_carry[0]),
 .S(sel_shift_carry),
 .O(sel_carry[1]) );

 MUXCY sel_arith_muxcy ( 
 .DI(arith_carry),
 .CI(sel_carry[1]),
 .S(sel_arith_carry),
 .O(sel_carry[2]) );

 MUXCY sel_parity_muxcy ( 
 .DI(parity),
 .CI(sel_carry[2]),
 .S(sel_parity),
 .O(sel_carry[3]) );

 XORCY carry_xor(
 .LI(1'b0),
 .CI(sel_carry[3]),
 .O(carry_fast_route));
             
 FDRE carry_flag_flop ( 
 .D(carry_fast_route),
 .Q(carry_flag),
 .CE(flag_enable),
 .R(internal_reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// The Program Counter
//
// Definition of a 10-bit counter which can be loaded from two sources
//
////////////////////////////////////////////////////////////////////////////////////
//	

 INV invert_enable(// Inverter should be implemented in the CE to flip flops
 .I(t_state),
 .O(pc_enable)); 
 
 // pc_loop

 // synthesis translate_off 
 defparam vector_select_mux_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_0 ( 
 .I0(instruction[15]),
 .I1(instruction[0]),
 .I2(stack_pop_data[0]), 
 .O(pc_vector[0]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_0(
 .I0(normal_count),
 .I1(inc_pc_vector[0]),
 .I2(pc[0]),
 .O(pc_value[0]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_0 ( 
 .D(inc_pc_value[0]),
 .Q(pc[0]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_0 ( 
 .DI(1'b0),
 .CI(instruction[13]),
 .S(pc_vector[0]),
 .O(pc_vector_carry[0]));

 XORCY pc_vector_xor_0 ( 
 .LI(pc_vector[0]),
 .CI(instruction[13]),
 .O(inc_pc_vector[0]));

 MUXCY pc_value_muxcy_0 ( 
 .DI(1'b0),
 .CI(normal_count),
 .S(pc_value[0]),
 .O(pc_value_carry[0]));

 XORCY pc_value_xor_0 ( 
 .LI(pc_value[0]),
 .CI(normal_count),
 .O(inc_pc_value[0]));

 // synthesis translate_off 
 defparam vector_select_mux_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_1 ( 
 .I0(instruction[15]),
 .I1(instruction[1]),
 .I2(stack_pop_data[1]), 
 .O(pc_vector[1]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_1(
 .I0(normal_count),
 .I1(inc_pc_vector[1]),
 .I2(pc[1]),
 .O(pc_value[1]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_1 ( 
 .D(inc_pc_value[1]),
 .Q(pc[1]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_1 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[0]),
 .S(pc_vector[1]),
 .O(pc_vector_carry[1]));

 XORCY pc_vector_xor_1 ( 
 .LI(pc_vector[1]),
 .CI(pc_vector_carry[0]),
 .O(inc_pc_vector[1]));

 MUXCY pc_value_muxcy_1 ( 
 .DI(1'b0),
 .CI(pc_value_carry[0]),
 .S(pc_value[1]),
 .O(pc_value_carry[1]));

 XORCY pc_value_xor_1 ( 
 .LI(pc_value[1]),
 .CI(pc_value_carry[0]),
 .O(inc_pc_value[1]));
 
 // synthesis translate_off 
 defparam vector_select_mux_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_2 ( 
 .I0(instruction[15]),
 .I1(instruction[2]),
 .I2(stack_pop_data[2]), 
 .O(pc_vector[2]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_2(
 .I0(normal_count),
 .I1(inc_pc_vector[2]),
 .I2(pc[2]),
 .O(pc_value[2]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_2 ( 
 .D(inc_pc_value[2]),
 .Q(pc[2]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_2 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[1]),
 .S(pc_vector[2]),
 .O(pc_vector_carry[2]));

 XORCY pc_vector_xor_2 ( 
 .LI(pc_vector[2]),
 .CI(pc_vector_carry[1]),
 .O(inc_pc_vector[2]));

 MUXCY pc_value_muxcy_2 ( 
 .DI(1'b0),
 .CI(pc_value_carry[1]),
 .S(pc_value[2]),
 .O(pc_value_carry[2]));

 XORCY pc_value_xor_2 ( 
 .LI(pc_value[2]),
 .CI(pc_value_carry[1]),
 .O(inc_pc_value[2]));
 
 // synthesis translate_off 
 defparam vector_select_mux_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_3 ( 
 .I0(instruction[15]),
 .I1(instruction[3]),
 .I2(stack_pop_data[3]), 
 .O(pc_vector[3]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_3(
 .I0(normal_count),
 .I1(inc_pc_vector[3]),
 .I2(pc[3]),
 .O(pc_value[3]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_3 ( 
 .D(inc_pc_value[3]),
 .Q(pc[3]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_3 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[2]),
 .S(pc_vector[3]),
 .O(pc_vector_carry[3]));

 XORCY pc_vector_xor_3 ( 
 .LI(pc_vector[3]),
 .CI(pc_vector_carry[2]),
 .O(inc_pc_vector[3]));

 MUXCY pc_value_muxcy_3 ( 
 .DI(1'b0),
 .CI(pc_value_carry[2]),
 .S(pc_value[3]),
 .O(pc_value_carry[3]));

 XORCY pc_value_xor_3 ( 
 .LI(pc_value[3]),
 .CI(pc_value_carry[2]),
 .O(inc_pc_value[3]));
 
 // synthesis translate_off 
 defparam vector_select_mux_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_4 ( 
 .I0(instruction[15]),
 .I1(instruction[4]),
 .I2(stack_pop_data[4]), 
 .O(pc_vector[4]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_4(
 .I0(normal_count),
 .I1(inc_pc_vector[4]),
 .I2(pc[4]),
 .O(pc_value[4]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_4 (