.D(inc_pc_value[4]),
 .Q(pc[4]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_4 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[3]),
 .S(pc_vector[4]),
 .O(pc_vector_carry[4]));

 XORCY pc_vector_xor_4 ( 
 .LI(pc_vector[4]),
 .CI(pc_vector_carry[3]),
 .O(inc_pc_vector[4]));

 MUXCY pc_value_muxcy_4 ( 
 .DI(1'b0),
 .CI(pc_value_carry[3]),
 .S(pc_value[4]),
 .O(pc_value_carry[4]));

 XORCY pc_value_xor_4 ( 
 .LI(pc_value[4]),
 .CI(pc_value_carry[3]),
 .O(inc_pc_value[4]));
 
 // synthesis translate_off 
 defparam vector_select_mux_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_5 ( 
 .I0(instruction[15]),
 .I1(instruction[5]),
 .I2(stack_pop_data[5]), 
 .O(pc_vector[5]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_5(
 .I0(normal_count),
 .I1(inc_pc_vector[5]),
 .I2(pc[5]),
 .O(pc_value[5]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_5 ( 
 .D(inc_pc_value[5]),
 .Q(pc[5]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_5 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[4]),
 .S(pc_vector[5]),
 .O(pc_vector_carry[5]));

 XORCY pc_vector_xor_5 ( 
 .LI(pc_vector[5]),
 .CI(pc_vector_carry[4]),
 .O(inc_pc_vector[5]));

 MUXCY pc_value_muxcy_5 ( 
 .DI(1'b0),
 .CI(pc_value_carry[4]),
 .S(pc_value[5]),
 .O(pc_value_carry[5]));

 XORCY pc_value_xor_5 ( 
 .LI(pc_value[5]),
 .CI(pc_value_carry[4]),
 .O(inc_pc_value[5]));
 
 // synthesis translate_off 
 defparam vector_select_mux_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_6 ( 
 .I0(instruction[15]),
 .I1(instruction[6]),
 .I2(stack_pop_data[6]), 
 .O(pc_vector[6]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_6(
 .I0(normal_count),
 .I1(inc_pc_vector[6]),
 .I2(pc[6]),
 .O(pc_value[6]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_6 ( 
 .D(inc_pc_value[6]),
 .Q(pc[6]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_6 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[5]),
 .S(pc_vector[6]),
 .O(pc_vector_carry[6]));

 XORCY pc_vector_xor_6 ( 
 .LI(pc_vector[6]),
 .CI(pc_vector_carry[5]),
 .O(inc_pc_vector[6]));

 MUXCY pc_value_muxcy_6 ( 
 .DI(1'b0),
 .CI(pc_value_carry[5]),
 .S(pc_value[6]),
 .O(pc_value_carry[6]));

 XORCY pc_value_xor_6 ( 
 .LI(pc_value[6]),
 .CI(pc_value_carry[5]),
 .O(inc_pc_value[6]));
     
 // synthesis translate_off 
 defparam vector_select_mux_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_7 ( 
 .I0(instruction[15]),
 .I1(instruction[7]),
 .I2(stack_pop_data[7]), 
 .O(pc_vector[7]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_7(
 .I0(normal_count),
 .I1(inc_pc_vector[7]),
 .I2(pc[7]),
 .O(pc_value[7]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_7 ( 
 .D(inc_pc_value[7]),
 .Q(pc[7]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_7 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[6]),
 .S(pc_vector[7]),
 .O(pc_vector_carry[7]));

 XORCY pc_vector_xor_7 ( 
 .LI(pc_vector[7]),
 .CI(pc_vector_carry[6]),
 .O(inc_pc_vector[7]));

 MUXCY pc_value_muxcy_7 ( 
 .DI(1'b0),
 .CI(pc_value_carry[6]),
 .S(pc_value[7]),
 .O(pc_value_carry[7]));

 XORCY pc_value_xor_7 ( 
 .LI(pc_value[7]),
 .CI(pc_value_carry[6]),
 .O(inc_pc_value[7]));
 
 // synthesis translate_off 
 defparam vector_select_mux_8.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_8 ( 
 .I0(instruction[15]),
 .I1(instruction[8]),
 .I2(stack_pop_data[8]), 
 .O(pc_vector[8]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_8.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_8(
 .I0(normal_count),
 .I1(inc_pc_vector[8]),
 .I2(pc[8]),
 .O(pc_value[8]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_8 ( 
 .D(inc_pc_value[8]),
 .Q(pc[8]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_8 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[7]),
 .S(pc_vector[8]),
 .O(pc_vector_carry[8]));

 XORCY pc_vector_xor_8 ( 
 .LI(pc_vector[8]),
 .CI(pc_vector_carry[7]),
 .O(inc_pc_vector[8]));

 MUXCY pc_value_muxcy_8 ( 
 .DI(1'b0),
 .CI(pc_value_carry[7]),
 .S(pc_value[8]),
 .O(pc_value_carry[8]));

 XORCY pc_value_xor_8 ( 
 .LI(pc_value[8]),
 .CI(pc_value_carry[7]),
 .O(inc_pc_value[8]));
 
 // synthesis translate_off 
 defparam vector_select_mux_9.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_9 ( 
 .I0(instruction[15]),
 .I1(instruction[9]),
 .I2(stack_pop_data[9]), 
 .O(pc_vector[9]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_9.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_9(
 .I0(normal_count),
 .I1(inc_pc_vector[9]),
 .I2(pc[9]),
 .O(pc_value[9]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_9 ( 
 .D(inc_pc_value[9]),
 .Q(pc[9]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 XORCY pc_vector_xor_high ( 
 .LI(pc_vector[9]),
 .CI(pc_vector_carry[8]),
 .O(inc_pc_vector[9]));

 XORCY pc_value_xor_high ( 
 .LI(pc_value[9]),
 .CI(pc_value_carry[8]),
 .O(inc_pc_value[9]));

 //end pc_loop;
 			
 assign address = pc;
//
////////////////////////////////////////////////////////////////////////////////////
//
// Register Bank and second operand selection.
//
// Definition of an 8-bit dual port RAM with 16 locations 
// including write enable decode.
//
// Outputs are assigned to PORT_ID and OUT_PORT.
//
////////////////////////////////////////////////////////////////////////////////////
//	
 // Forming decode signal

 // synthesis translate_off 
 defparam register_type_lut.INIT = 16'h0145;
 // synthesis translate_on 
 LUT4 register_type_lut ( 
 .I0(active_interrupt),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(register_type ))/* synthesis xc_props = "INIT=0145"*/;

 FD register_write_flop ( 
 .D(register_type),
 .Q(register_write),
 .C(clk));

 // synthesis translate_off 
 defparam register_enable_lut.INIT = 4'h8;
 // synthesis translate_on 
 LUT2 register_enable_lut ( 
 .I0(t_state),
 .I1(register_write),
 .O(register_enable))/* synthesis xc_props = "INIT=8"*/;

 //reg_loop

 // synthesis translate_off 
 defparam reg_loop_register_bit_0.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_0 ( 
 .D(alu_result[0]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[0]),
 .DPO(sy[0]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_0 ( 
 .I0(instruction[12]),
 .I1(instruction[0]),
 .I2(sy[0]),
 .O(second_operand[0]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam reg_loop_register_bit_1.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_1 ( 
 .D(alu_result[1]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[1]),
 .DPO(sy[1]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_1 ( 
 .I0(instruction[12]),
 .I1(instruction[1]),
 .I2(sy[1]),
 .O(second_operand[1]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam reg_loop_register_bit_2.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_2 ( 
 .D(alu_result[2]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[2]),
 .DPO(sy[2]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_2 ( 
 .I0(instruction[12]),
 .I1(instruction[2]),
 .I2(sy[2]),
 .O(second_operand[2]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam reg_loop_register_bit_3.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_3 ( 
 .D(alu_result[3]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[3]),
 .DPO(sy[3]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_3 ( 
 .I0(instruction[12]),
 .I1(instruction[3]),
 .I2(sy[3]),
 .O(second_operand[3]))/* synthesis xc_props = "INIT=E4"*/;
  
 // synthesis translate_off 
 defparam reg_loop_register_bit_4.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_4 ( 
 .D(alu_result[4]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[4]),
 .DPO(sy[4]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_4 ( 
 .I0(instruction[12]),
 .I1(instruction[4]),
 .I2(sy[4]),
 .O(second_operand[4]))/* synthesis xc_props = "INIT=E4"*/;
 
 // synthesis translate_off 
 defparam reg_loop_register_bit_5.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_5 ( 
 .D(alu_result[5]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[5]),
 .DPO(sy[5]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_5 ( 
 .I0(instruction[12]),
 .I1(instruction[5]),
 .I2(sy[5]),
 .O(second_operand[5]))/* synthesis xc_props = "INIT=E4"*/;
 
 // synthesis translate_off 
 defparam reg_loop_register_bit_6.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_6 ( 
 .D(alu_result[6]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),
 .A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[6]),
 .DPO(sy[6]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_6 ( 
 .I0(instruction[12]),
 .I1(instruction[6]),
 .I2(sy[6]),
 .O(second_operand[6]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam reg_loop_register_bit_7.INIT = 16'h0000;
 // synthesis translate_on 
 RAM16X1D reg_loop_register_bit_7 ( 
 .D(alu_result[7]),
 .WE(register_enable),
 .WCLK(clk),
 .A0(instruction[8]),