.A1(instruction[9]),
 .A2(instruction[10]),
 .A3(instruction[11]),
 .DPRA0(instruction[4]),
 .DPRA1(instruction[5]),
 .DPRA2(instruction[6]),
 .DPRA3(instruction[7]),
 .SPO(sx[7]),
 .DPO(sy[7]))/* synthesis xc_props = "INIT=0000"*/;

 // synthesis translate_off 
 defparam operand_select_mux_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 operand_select_mux_7 ( 
 .I0(instruction[12]),
 .I1(instruction[7]),
 .I2(sy[7]),
 .O(second_operand[7]))/* synthesis xc_props = "INIT=E4"*/;
    
 assign out_port = sx;
 assign port_id = second_operand;
//
////////////////////////////////////////////////////////////////////////////////////
//
// Store Memory
//
// Definition of an 8-bit single port RAM with 64 locations 
// including write enable decode.
//
////////////////////////////////////////////////////////////////////////////////////
//	
 // Forming decode signal

 // synthesis translate_off 
 defparam memory_type_lut.INIT = 16'h0400;
 // synthesis translate_on 
 LUT4 memory_type_lut ( 
 .I0(active_interrupt),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(memory_type ))/* synthesis xc_props = "INIT=0400"*/;

 FD memory_write_flop ( 
 .D(memory_type),
 .Q(memory_write),
 .C(clk));

 // synthesis translate_off 
 defparam memory_enable_lut.INIT = 16'h8000;
 // synthesis translate_on 
 LUT4 memory_enable_lut ( 
 .I0(t_state),
 .I1(instruction[13]),
 .I2(instruction[14]),
 .I3(memory_write),
 .O(memory_enable ))/* synthesis xc_props = "INIT=8000"*/;

 // store_loop

 // synthesis translate_off 
 defparam memory_bit_0.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_0 ( 
 .D(sx[0]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[0]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_0 ( 
 .D(memory_data[0]),
 .Q(store_data[0]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_1.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_1 ( 
 .D(sx[1]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[1]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_1 ( 
 .D(memory_data[1]),
 .Q(store_data[1]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_2.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_2 ( 
 .D(sx[2]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[2]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_2 ( 
 .D(memory_data[2]),
 .Q(store_data[2]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_3.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_3 ( 
 .D(sx[3]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[3]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_3 ( 
 .D(memory_data[3]),
 .Q(store_data[3]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_4.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_4 ( 
 .D(sx[4]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[4]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_4 ( 
 .D(memory_data[4]),
 .Q(store_data[4]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_5.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_5 ( 
 .D(sx[5]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[5]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_5 ( 
 .D(memory_data[5]),
 .Q(store_data[5]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_6.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_6 ( 
 .D(sx[6]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[6]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_6 ( 
 .D(memory_data[6]),
 .Q(store_data[6]),
 .C(clk));

 // synthesis translate_off 
 defparam memory_bit_7.INIT = 64'h0000000000000000;
 // synthesis translate_on 
 RAM64X1S memory_bit_7 ( 
 .D(sx[7]),
 .WE(memory_enable),
 .WCLK(clk),
 .A0(second_operand[0]),
 .A1(second_operand[1]),
 .A2(second_operand[2]),
 .A3(second_operand[3]),
 .A4(second_operand[4]),
 .A5(second_operand[5]),
 .O(memory_data[7]))/* synthesis xc_props = "INIT=0000000000000000"*/;

 FD store_flop_7 ( 
 .D(memory_data[7]),
 .Q(store_data[7]),
 .C(clk));
      
//
////////////////////////////////////////////////////////////////////////////////////
//
// Logical operations
//
// Definition of AND, OR, XOR and LOAD functions which also provides TEST.
// Includes pipeline stage used to form ALU multiplexer including decode.
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam sel_logical_lut.INIT = 16'hFFE2;
 // synthesis translate_on 
 LUT4 sel_logical_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(sel_logical ))/* synthesis xc_props = "INIT=FFE2"*/;

 // logical_loop

 // synthesis translate_off 
 defparam logical_lut_0.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_0 ( 
 .I0(second_operand[0]),
 .I1(sx[0]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[0]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_0 ( 
 .D(logical_value[0]),
 .Q(logical_result[0]),
 .R(sel_logical),
 .C(clk));

 // synthesis translate_off 
 defparam logical_lut_1.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_1 ( 
 .I0(second_operand[1]),
 .I1(sx[1]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[1]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_1 ( 
 .D(logical_value[1]),
 .Q(logical_result[1]),
 .R(sel_logical),
 .C(clk));
 
 // synthesis translate_off 
 defparam logical_lut_2.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_2 ( 
 .I0(second_operand[2]),
 .I1(sx[2]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[2]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_2 ( 
 .D(logical_value[2]),
 .Q(logical_result[2]),
 .R(sel_logical),
 .C(clk));
 
 // synthesis translate_off 
 defparam logical_lut_3.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_3 ( 
 .I0(second_operand[3]),
 .I1(sx[3]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[3]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_3 ( 
 .D(logical_value[3]),
 .Q(logical_result[3]),
 .R(sel_logical),
 .C(clk));

 // synthesis translate_off 
 defparam logical_lut_4.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_4 ( 
 .I0(second_operand[4]),
 .I1(sx[4]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[4]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_4 ( 
 .D(logical_value[4]),
 .Q(logical_result[4]),
 .R(sel_logical),
 .C(clk));

 // synthesis translate_off 
 defparam logical_lut_5.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_5 ( 
 .I0(second_operand[5]),
 .I1(sx[5]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[5]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_5 ( 
 .D(logical_value[5]),
 .Q(logical_result[5]),
 .R(sel_logical),
 .C(clk));

 // synthesis translate_off 
 defparam logical_lut_6.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_6 ( 
 .I0(second_operand[6]),
 .I1(sx[6]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[6]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_6 ( 
 .D(logical_value[6]),
 .Q(logical_result[6]),
 .R(sel_logical),
 .C(clk));

 // synthesis translate_off 
 defparam logical_lut_7.INIT = 16'h6E8A;
 // synthesis translate_on 
 LUT4 logical_lut_7 ( 
 .I0(second_operand[7]),
 .I1(sx[7]),
 .I2(instruction[13]),
 .I3(instruction[14]),
 .O(logical_value[7]))/* synthesis xc_props = "INIT=6E8A"*/;

 FDR logical_flop_7 ( 
 .D(logical_value[7]),
 .Q(logical_result[7]),
 .R(sel_logical),
 .C(clk));
     
//
////////////////////////////////////////////////////////////////////////////////////
//
// Shift and Rotate operations
//
// Includes pipeline stage used to form ALU multiplexer including decode.
//
////////////////////////////////////////////////////////////////////////////////////
//
 INV sel_shift_inv( // Inverter should be implemented in the reset to flip flops
 .I(instruction[17]),
 .O(sel_shift)); 

 // Bit to input to shift register

 // synthesis translate_off 
 defparam high_shift_in_lut.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 high_shift_in_lut ( 
 .I0(instruction[1]),
 .I1(sx[0]),
 .I2(instruction[0]),
 .O(high_shift_in ))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam low_shift_in_lut.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 low_shift_in_lut ( 
 .I0(instruction[1]),
 .I1(carry_flag),
 .I2(sx[7]),
 .O(low_shift_in))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5 ( 
 .I1(high_shift_in),
 .I0(low_shift_in),
 .S(instruction[2]),
 .O(shift_in )); 

 // Forming shift carry signal

 // synthesis translate_off 
 defparam shift_carry_lut.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_carry_lut ( 
 .I0(instruction[3]),
 .I1(sx[7]),
 .I2(sx[0]),
 .O(shift_carry_value ))/* synthesis xc_props = "INIT=E4"*/;
					 
 FD pipeline_bit ( 
 .D(shift_carry_value),
 .Q(shift_carry),
 .C(clk));

// shift_loop

 // synthesis translate_off 
 defparam shift_mux_lut_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_0 ( 
 .I0(instruction[3]),
 .I1(shift_in),
 .I2(sx[1]),
 .O(shift_value[0]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_0 ( 
 .D(shift_value[0]),
 .Q(shift_result[0]),
 .R(sel_shift),
 .C(clk));
 	 
 // synthesis translate_off 
 defparam shift_mux_lut_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_1 ( 
 .I0(instruction[3]),
 .I1(sx[0]),
 .I2(sx[2]),
 .O(shift_value[1]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_1 ( 
 .D(shift_value[1]),
 .Q(shift_result[1]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_2 ( 
 .I0(instruction[3]),
 .I1(sx[1]),
 .I2(sx[3]),
 .O(shift_value[2]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_2 ( 
 .D(shift_value[2]),
 .Q(shift_result[2]),
 .R(sel_shift),
 .C(clk));
 	 
 // synthesis translate_off 
 defparam shift_mux_lut_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_3 ( 
 .I0(instruction[3]),
 .I1(sx[2]),
 .I2(sx[4]),
 .O(shift_value[3]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_3 ( 
 .D(shift_value[3]),
 .Q(shift_result[3]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_4 ( 
 .I0(instruction[3]),
 .I1(sx[3]),
 .I2(sx[5]),
 .O(shift_value[4]))/* synthesis xc_props = "INIT=E4"*/;