FDR shift_flop_4 ( 
 .D(shift_value[4]),
 .Q(shift_result[4]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_5 ( 
 .I0(instruction[3]),
 .I1(sx[4]),
 .I2(sx[6]),
 .O(shift_value[5]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_5 ( 
 .D(shift_value[5]),
 .Q(shift_result[5]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_6 ( 
 .I0(instruction[3]),
 .I1(sx[5]),
 .I2(sx[7]),
 .O(shift_value[6]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_6 ( 
 .D(shift_value[6]),
 .Q(shift_result[6]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_7 ( 
 .I0(instruction[3]),
 .I1(sx[6]),
 .I2(shift_in),
 .O(shift_value[7]) )/* synthesis xc_props = "INIT=E4"*/;
	 
 FDR shift_flop_7 ( 
 .D(shift_value[7]),
 .Q(shift_result[7]),
 .R(sel_shift),
 .C(clk));

//
////////////////////////////////////////////////////////////////////////////////////
//
// Arithmetic operations
//
// Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE.
// Includes pipeline stage used to form ALU multiplexer including decode.
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam sel_arith_lut.INIT = 8'h1F;
 // synthesis translate_on 
 LUT3 sel_arith_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .O(sel_arith))/* synthesis xc_props = "INIT=1F"*/; 
 
 //arith_loop 

 // synthesis translate_off 
 defparam arith_carry_in_lut.INIT = 8'h6C;
 // synthesis translate_on 
 LUT3 arith_carry_in_lut ( 
 .I0(instruction[13]),
 .I1(instruction[14]),
 .I2(carry_flag),
 .O(sel_arith_carry_in ))/* synthesis xc_props = "INIT=6C"*/;

 MUXCY arith_carry_in_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(sel_arith_carry_in),
 .O(arith_carry_in));

 MUXCY arith_muxcy_0 ( 
 .DI(sx[0]),
 .CI(arith_carry_in),
 .S(half_arith[0]),
 .O(arith_internal_carry[0]));
 
 XORCY arith_xor_0 ( 
 .LI(half_arith[0]),
 .CI(arith_carry_in),
 .O(arith_value[0]));

 // synthesis translate_off 
 defparam arith_lut_0.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_0 ( 
 .I0(sx[0]),
 .I1(second_operand[0]),
 .I2(instruction[14]),
 .O(half_arith[0]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_0 ( 
 .D(arith_value[0]),
 .Q(arith_result[0]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_1 ( 
 .DI(sx[1]),
 .CI(arith_internal_carry[0]),
 .S(half_arith[1]),
 .O(arith_internal_carry[1]));

 XORCY arith_xor_1 ( 
 .LI(half_arith[1]),
 .CI(arith_internal_carry[0]),
 .O(arith_value[1]));

 // synthesis translate_off 
 defparam arith_lut_1.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_1 ( 
 .I0(sx[1]),
 .I1(second_operand[1]),
 .I2(instruction[14]),
 .O(half_arith[1]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_1 ( 
 .D(arith_value[1]),
 .Q(arith_result[1]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_2 ( 
 .DI(sx[2]),
 .CI(arith_internal_carry[1]),
 .S(half_arith[2]),
 .O(arith_internal_carry[2]));

 XORCY arith_xor_2 ( 
 .LI(half_arith[2]),
 .CI(arith_internal_carry[1]),
 .O(arith_value[2]));

 // synthesis translate_off 
 defparam arith_lut_2.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_2 ( 
 .I0(sx[2]),
 .I1(second_operand[2]),
 .I2(instruction[14]),
 .O(half_arith[2]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_2 ( 
 .D(arith_value[2]),
 .Q(arith_result[2]),
 .R(sel_arith),
 .C(clk));
  
 MUXCY arith_muxcy_3 ( 
 .DI(sx[3]),
 .CI(arith_internal_carry[2]),
 .S(half_arith[3]),
 .O(arith_internal_carry[3]));

 XORCY arith_xor_3 ( 
 .LI(half_arith[3]),
 .CI(arith_internal_carry[2]),
 .O(arith_value[3]));

 // synthesis translate_off 
 defparam arith_lut_3.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_3 ( 
 .I0(sx[3]),
 .I1(second_operand[3]),
 .I2(instruction[14]),
 .O(half_arith[3]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_3 ( 
 .D(arith_value[3]),
 .Q(arith_result[3]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_4 ( 
 .DI(sx[4]),
 .CI(arith_internal_carry[3]),
 .S(half_arith[4]),
 .O(arith_internal_carry[4]));

 XORCY arith_xor_4 ( 
 .LI(half_arith[4]),
 .CI(arith_internal_carry[3]),
 .O(arith_value[4]));

 // synthesis translate_off 
 defparam arith_lut_4.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_4 ( 
 .I0(sx[4]),
 .I1(second_operand[4]),
 .I2(instruction[14]),
 .O(half_arith[4]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_4 ( 
 .D(arith_value[4]),
 .Q(arith_result[4]),
 .R(sel_arith),
 .C(clk));
  
 MUXCY arith_muxcy_5 ( 
 .DI(sx[5]),
 .CI(arith_internal_carry[4]),
 .S(half_arith[5]),
 .O(arith_internal_carry[5]));

 XORCY arith_xor_5 ( 
 .LI(half_arith[5]),
 .CI(arith_internal_carry[4]),
 .O(arith_value[5])); 	 

 // synthesis translate_off 
 defparam arith_lut_5.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_5 ( 
 .I0(sx[5]),
 .I1(second_operand[5]),
 .I2(instruction[14]),
 .O(half_arith[5]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_5 ( 
 .D(arith_value[5]),
 .Q(arith_result[5]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_6 ( 
 .DI(sx[6]),
 .CI(arith_internal_carry[5]),
 .S(half_arith[6]),
 .O(arith_internal_carry[6]));

 XORCY arith_xor_6 ( 
 .LI(half_arith[6]),
 .CI(arith_internal_carry[5]),
 .O(arith_value[6]));

 // synthesis translate_off 
 defparam arith_lut_6.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_6 ( 
 .I0(sx[6]),
 .I1(second_operand[6]),
 .I2(instruction[14]),
 .O(half_arith[6]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_6 ( 
 .D(arith_value[6]),
 .Q(arith_result[6]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_7 ( 
 .DI(sx[7]),
 .CI(arith_internal_carry[6]),
 .S(half_arith[7]),
 .O(arith_internal_carry[7]));

 XORCY arith_xor_7 ( 
 .LI(half_arith[7]),
 .CI(arith_internal_carry[6]),
 .O(arith_value[7]));

 // synthesis translate_off 
 defparam arith_carry_out_lut.INIT = 2'h2;
 // synthesis translate_on 
 LUT1 arith_carry_out_lut ( 
 .I0(instruction[14]),
 .O(invert_arith_carry ))/* synthesis xc_props = "INIT=2"*/;
 
  XORCY arith_carry_out_xor ( 
 .LI(invert_arith_carry),
 .CI(arith_internal_carry[7]),
 .O(arith_carry_out));

 // synthesis translate_off 
 defparam arith_lut_7.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_7 ( 
 .I0(sx[7]),
 .I1(second_operand[7]),
 .I2(instruction[14]),
 .O(half_arith[7]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_7 ( 
 .D(arith_value[7]),
 .Q(arith_result[7]),
 .R(sel_arith),
 .C(clk));
 
 FDR arith_carry_flop ( 
 .D(arith_carry_out),
 .Q(arith_carry),
 .R(sel_arith),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// ALU multiplexer
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam input_fetch_type_lut.INIT = 16'h0002;
 // synthesis translate_on 
 LUT4 input_fetch_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(input_fetch_type ))/* synthesis xc_props = "INIT=0002"*/;

 FD sel_group_flop ( 
 .D(input_fetch_type),
 .Q(sel_group),
 .C(clk));
 
 //alu_mux_loop 

 // synthesis translate_off 
 defparam or_lut_0.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_0 ( 
 .I0(logical_result[0]),
 .I1(arith_result[0]),
 .I2(shift_result[0]),
 .O(alu_group[0]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_0 ( 
 .I0(instruction[13]),
 .I1(in_port[0]),
 .I2(store_data[0]),
 .O(input_group[0]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_0 ( 
 .I1(input_group[0]),
 .I0(alu_group[0]),
 .S(sel_group),
 .O(alu_result[0]) ); 

 // synthesis translate_off 
 defparam or_lut_1.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_1 ( 
 .I0(logical_result[1]),
 .I1(arith_result[1]),
 .I2(shift_result[1]),
 .O(alu_group[1]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_1 ( 
 .I0(instruction[13]),
 .I1(in_port[1]),
 .I2(store_data[1]),
 .O(input_group[1]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_1 ( 
 .I1(input_group[1]),
 .I0(alu_group[1]),
 .S(sel_group),
 .O(alu_result[1]) ); 

 // synthesis translate_off 
 defparam or_lut_2.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_2 ( 
 .I0(logical_result[2]),
 .I1(arith_result[2]),
 .I2(shift_result[2]),
 .O(alu_group[2]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_2 ( 
 .I0(instruction[13]),
 .I1(in_port[2]),
 .I2(store_data[2]),
 .O(input_group[2]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_2 ( 
 .I1(input_group[2]),
 .I0(alu_group[2]),
 .S(sel_group),
 .O(alu_result[2]) ); 

 // synthesis translate_off 
 defparam or_lut_3.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_3 ( 
 .I0(logical_result[3]),
 .I1(arith_result[3]),
 .I2(shift_result[3]),
 .O(alu_group[3]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_3 ( 
 .I0(instruction[13]),
 .I1(in_port[3]),
 .I2(store_data[3]),
 .O(input_group[3]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_3 ( 
 .I1(input_group[3]),
 .I0(alu_group[3]),
 .S(sel_group),
 .O(alu_result[3]) ); 
  
 // synthesis translate_off 
 defparam or_lut_4.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_4 ( 
 .I0(logical_result[4]),
 .I1(arith_result[4]),
 .I2(shift_result[4]),
 .O(alu_group[4]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_4 ( 
 .I0(instruction[13]),
 .I1(in_port[4]),
 .I2(store_data[4]),
 .O(input_group[4]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_4 ( 
 .I1(input_group[4]),
 .I0(alu_group[4]),
 .S(sel_group),
 .O(alu_result[4]) ); 
 
  // synthesis translate_off 
 defparam or_lut_5.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_5 ( 
 .I0(logical_result[5]),
 .I1(arith_result[5]),
 .I2(shift_result[5]),
 .O(alu_group[5]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_5 ( 
 .I0(instruction[13]),
 .I1(in_port[5]),
 .I2(store_data[5]),
 .O(input_group[5]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_5 ( 
 .I1(input_group[5]),
 .I0(alu_group[5]),
 .S(sel_group),
 .O(alu_result[5]) ); 

 // synthesis translate_off 
 defparam or_lut_6.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_6 ( 
 .I0(logical_result[6]),
 .I1(arith_result[6]),
 .I2(shift_result[6]),
 .O(alu_group[6]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_6 ( 
 .I0(instructio